Encoding circuit for transform coding of a picture signal and decoding circuit for decoding said signal

Abstract

An encoding circuit transforms a picture signal into blocks of, for example, 8*8 coefficients, in which each block of coefficients is read motion- adaptively. In the case of motion within a sub-picture, the block of coefficients is read in such an order that the obtained series of coefficients includes, as it were, two interleaved sub-series. The first series starts with a dc component. In a first embodiment, the second series starts with the most relevant motion coefficient. In a second embodiment, two interlaced sub-fields are separately transformed and the second series also starts with a dc coefficient. As a result, the coefficients are transmitted as much as possible in their order of significance. This particularly produces the largest possible clusters of zero value coefficients. Such clusters are transmitted as one compact run-length code so that an effective bit rate reduction is achieved, also for moving pictures.

1 . An encoding circuit for transform coding of a picture signal, comprising: 
 means for partitioning pictures into sub-pictures,    a transform circuit for transforming each sub-picture into a two-dimensional block of contiguous coefficients,    a motion detector receiving the sub-pictures and generating a motion signal when noticeable motion has been detected within the sub-picture,    scanning means for reading the block of coefficients in accordance with a scanning pattern dependent on the motion signal and for converting them into a serial sequence of coefficients,    characterized in that the scanning pattern provides at least one jump to a predetermined coefficient which is not contiguous to a previously read coefficient.    
     
     
         2 . An encoding circuit as claimed in  claim 1 , characterized in that the predetermined coefficient is representative of the presence of motion in the sub-picture.  
     
     
         3 . An encoding circuit as claimed in  claim 1 , in which the sub-picture comprises two interlaced sub-fields, characterized in that the transform circuit is adapted to partition the block of coefficients into sub-blocks by separately transforming the sub-fields and in that the predetermined coefficient forms part of a different sub-block than the previously read coefficients.  
     
     
         4 . An encoding circuit as claimed in  claim 3 , characterized in that the predetermined coefficient is the dc coefficient of the relevant sub-block.  
     
     
         5 . An encoding circuit as claimed in  claim 3 , characterized in that the scanning means are further adapted to read the separate sub-blocks in accordance with a zigzag pattern.  
     
     
         6 . An encoding circuit as claimed in  claim 3 , characterized in that the scanning means are further adapted to read coefficients of the two sub-blocks alternately.  
     
     
         7 . An encoding circuit as claimed in  claim 3 , characterized in that it is further provided with means for converting the dc coefficients of the two sub-blocks into a difference coefficient which represents the difference of said dc coefficients.  
     
     
         8 . A decoding circuit for decoding a transformed picture signal supplied by an encoding circuit as claimed in  claim 1  or  2 , comprising: 
 means for regenerating the motion signal,  
 storage means for storing a serial sequence of coefficients in accordance with a storage pattern dependent on the motion signal in a two-dimensional block of contiguous addressable memory locations,  
 an inverse transform circuit for transforming the coefficients stored in the block into a sub-picture,  
 characterized in that the storage pattern jumps by at least one step to a predetermined memory location which is not contiguous to previously addressed memory locations.  
 
     
     
         9 . A decoding circuit as claimed in  claim 8  for decoding a transformed picture signal which is supplied by an encoding circuit as claimed in any one of claims  3 - 6 , characterized in that the inverse transform circuit is adapted to partition the block of coefficients into two sub-blocks and to transform them separately into two interlaced sub-fields, and in that the predetermined memory location forms part of a different sub-block than the previously addressed memory locations.  
     
     
         10 . A decoding circuit as claimed in  claim 9  for decoding a transformed picture signal from an encoding circuit as claimed in  claim 7 , characterized in that the decoding circuit is further provided with means for regaining the two dc coefficients from the received difference coefficient.  
     
     
         11 . A transmitter of television signals, including an encoding circuit as claimed in any one of claims  1 - 7 .  
     
     
         12 . A receiver of television signals, including a decoding circuit as claimed in  claim 8 ,  9  or  10 .  
     
     
         13 . A video recorder for recording and displaying televison signals, including an encoding circuit as claimed in any one of claims  1 - 7  and a decoding circuit as claimed in  claim 8 ,  9  or  10 .