Semiconductor integral circuit

Abstract

In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or the like is reduced. The semiconductor integral circuit has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. The semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of the MOS transistor of the analog circuit is set smaller than the absolute value of the threshold value of the MOS transistor of the logic circuit.

What is claimed is:  
     
         1 . A semiconductor integral circuit comprising: 
 an analog circuit which changes linearly a voltage of an input signal and causes an amount of a current flowing through said analog circuit to change in accordance with said change in said voltage of said input signal, said analog circuit having a MOS transistor; and    a logic circuit to which an input signal having a first or second voltage is input and which outputs an output signal having said first or second voltage in response to said first or second voltage of said input signal, said logic circuit having a MOS transistor,    wherein an absolute value of a threshold value of said MOS transistor of said analog circuit is set smaller than an absolute value of a threshold value of said MOS transistor of said logic circuit.    
     
     
         2 . A semiconductor integral circuit as claimed in  claim 1 , wherein said analog circuit has a first N-channel type MOS transistor and a first P-channel type MOS transistor, and said logic circuit has a second N-channel type MOS transistor and a second P-channel type MOS transistor, said semiconductor integral circuit satisfying relations Vtn 1 +|Vtp 1 |<Vcc, Vcc<Vtn 2 +|Vtp 2 |<2Vcc, Vtn 2 <Vcc, and |Vtp 2 |<Vcc, where Vtn 1 , Vtp 1 , Vtn 2 , and Vtp 2  denote threshold values of said first N-channel MOS transistor, said first P-charmel MOS transistor, said second N-channel MOS transistor and said second P-channel MOS transistor, respectively, and Vcc and GND denote said first voltage and said second voltage, respectively.  
     
     
         3 . A semiconductor integral circuit as claimed in  claim 2 , wherein said threshold value of each of said transistors is set by controlling an amount of ions injected into a semiconductor substrate in which each of said transistors is formed.  
     
     
         4 . A semiconductor integral circuit as claimed in  claim 2 , wherein said first N-channel type MOS transistor, said second N-channel first type MOS transistor, said first P-channel type MOS transistor, and said second P-channel type MOS transistor are formed in a first P-type semiconductor substrate, a second P-type semiconductor substrate, a first N-type semiconductor substrate, and a second N-type semiconductor substrate, respectively,  
       and wherein each of said semiconductor substrates is biased to a prescribed voltage such that said first P-type semiconductor substrate is biased to a first prescribed voltage that is higher than a second prescribed voltage to which said second P-type semiconductor substrate is biased and such that an absolute value of a third prescribed voltage to which said first N-type semiconductor substrate is biased is smaller than an absolute value of a fourth prescribed voltage to which said second N-type semiconductor substrate is biased.  
     
     
         5 . A semiconductor integral circuit as claimed in  claim 4 , satisfying relations VBB 1 ≧GND, VPP 1 ≦Vcc, VBB 2 ≦GND, and VPP 2 ≧Vcc, where VBB 1 , VBB 2 , VPP 1 , and VPP 2  denote voltages biased to said first P-type semiconductor substrate, said second P-type semiconductor substrate, said first N-type semiconductor substrate, and said second N-type semiconductor substrate, respectively.  
     
     
         6 . A semiconductor integral circuit driven by a first voltage and a second voltage, comprising: 
 an analog circuit to which an analog input signal having a voltage that changes continuously between said first voltage and said second voltage is input and which outputs an analog output signal in response to said analog input signal, said analog circuit having a MOS transistor; and    a logic circuit to which a first logic level input signal having said first voltage or a second logic level input signal having said second voltage is input and which outputs a first logic level output signal in response to said first logic level input signal or a second logic level output signal in response to said second logic level input signal, said logic circuit having a MOS transistor,    wherein an absolute value of a threshold value of said MOS transistor of said analog circuit is set smaller than an absolute value of a threshold value of said MOS transistor of said logic circuit.    
     
     
         7 . A semiconductor integral circuit as claimed in  claim 6 , wherein said analog circuit has a first N-channel type MOS transistor and a first P-channel type MOS transistor and said logic circuit has a second N-channel type MOS transistor and a second P-channel type MOS transistor, said semiconductor integral circuit satisfying relations Vtn 1 +|Vtp 1 |<Vcc, Vcc<Vtn 2 +|Vtp 2 |<2Vcc, Vtn 2 <Vcc, and |Vtp 2 |<Vcc, where Vtn 1 , Vtp 1 , Vtn 2 , and Vtp 2  denote threshold values of said first N-channel MOS transistor, said first P-channel MOS transistor, said second N-channel MOS transistor and said second P-channel MOS transistor, respectively, and Vcc and GND denote said first voltage and said second voltage, respectively.  
     
     
         8 . A semiconductor integral circuit as claimed in  claim 7 , wherein said threshold value of each of said transistors is set by controlling an amount of ions injected into a semiconductor substrate in which each of said transistors is formed.  
     
     
         9 . A semiconductor integral circuit as claimed in  claim 7 , wherein said first N-channel type MOS transistor, said second N-channel first type MOS transistor, said first P-channel type MOS transistor, and said second P-channel type MOS transistor are formed in a first P-type semiconductor substrate, a second P-type semiconductor substrate, a first N-type semiconductor substrate, and a second N-type semiconductor substrate, respectively,  
       and wherein each of said semiconductor substrates is biased to a prescribed voltage such that said first P-type semiconductor substrate is biased to a first prescribed voltage that is higher than a second prescribed voltage to which said second P-type semiconductor substrate is biased and such that an absolute value of a third prescribed voltage to which said first N-type semiconductor substrate is biased is smaller than an absolute value of a fourth prescribed voltage to which said second N-type semiconductor substrate is biased.  
     
     
         10 . A semiconductor integral circuit as claimed in  claim 9 , satisfying relations VBB 1 ≧GND, VPP 1 ≦Vcc, VBB 2 ≦GND, and VPP 2 ≧Vcc, where VBB 1 , VBB 2 , VPP 1 , and VPP 2  denote voltages biased to said first P-type semiconductor substrate, said second P-type semiconductor substrate, said first N-type semiconductor substrate, and said second N-type semiconductor substrate, respectively.