Mosfet gate electrodes having performance tuned work functions and methods of making same

Abstract

An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.

What is claimed is:  
     
         1 . A FET of a first conductivity type, comprising: 
 a source terminal; a drain terminal; a gate insulator; and    a gate electrode comprising a metal having a work function approximately equal to the work function of polysilicon doped with a first conductivity type dopant.    
     
     
         2 . The FET of  claim 1 , wherein the FET is an NFET, and the metal is tantalum.  
     
     
         3 . The FET of  claim 1 , wherein the FET is a PFET and the metal is tantalum nitride.  
     
     
         4 . The FET of  claim 1 , further comprising a barrier layer subjacent the metal, wherein the barrier layer is less than or equal to 5 nm and the atomic per cent of nitrogen in the barrier layer is in the range of 0% to 65%.  
     
     
         5 . The FET of  claim 4 , wherein the barrier layer is titanium nitride.  
     
     
         6 . The FET of  claim 4 , wherein the barrier layer is tantalum nitride.  
     
     
         7 . The FET of  claim 1 , wherein the FET is an NFET and the gate electrode has a work function approximately equal to a work function of n-doped polysilicon.  
     
     
         8 . The FET of  claim 1 , wherein the FET is a PFET and the gate electrode has a work function approximately equal to a work function of p-doped polysilicon.  
     
     
         5 . The FET of  claim 4 , wherein the gate electrode further comprises a layer of copper superjacent the metal.  
     
     
         9 . An integrated circuit, comprising: 
 a substrate;    a first FET of a first conductivity type formed on the substrate; and    a second FET of a second conductivity type formed on the substrate,    wherein the first FET has a first metal gate electrode, the second FET has a second metal gate electrode, and the first and second metal gate electrodes have different work functions.    
     
     
         10 . The integrated circuit of  claim 9 , wherein the first metal gate electrode and the second metal gate electrode have at least one element in common.  
     
     
         11 . The integrated circuit of  claim 9 , wherein the first metal gate electrode comprises tantalum, and the second metal gate electrode comprises tantalum nitride.  
     
     
         12 . The integrated circuit of  claim 11 , wherein the first FET is an n-channel FET, and the second FET is a p-channel FET.  
     
     
         13 . The integrated circuit of  claim 11 , further comprising a layer of copper over the first metal gate electrode; and a layer of copper over the second gate electrode.  
     
     
         14 . A method of making complementary FETs, comprising: 
 forming a first doped region of a first conductivity type in a substrate;    forming a second doped region of a second conductivity type in the substrate;    forming a gate insulator layer over the first and second doped regions;    depositing a layer of metal over the gate insulator layer, the metal having a first work function;    modifying a portion of the metal layer such that the modified portion has a second work function;    patterning the metal layer to form gate electrodes; and    forming source/drain junctions aligned to the gate electrodes.    
     
     
         15 . The method of  claim 14 , wherein depositing a layer of metal comprises depositing a layer of tantalum.  
     
     
         16 . The method of  claim 14 , wherein modifying a portion of the metal layer comprises: 
 forming a masking layer over the metal layer;    patterning the masking layer such that at least a first portion of the metal is exposed and a second portion is covered by the masking layer, the first portion being superjacent the second doped region;    chemically changing the work function of the first portion.    
     
     
         17 . The method of  claim 16 , wherein chemically changing the work function comprises nitridizing the first portion.  
     
     
         18 . The method of  claim 15 , wherein modifying a portion of the metal layer comprises converting a portion of the metal layer to tantalum nitride.  
     
     
         19 . The method of  claim 14 , further comprising forming a layer of a second metal over the first metal layer, including over the modified portion of the first metal layer.  
     
     
         20 . The method of  claim 19 , wherein the second metal comprises copper.  
     
     
         21 . The method of  claim 17 , wherein nitridizing comprises exposing tantalum to a nitrogen ambient at high temperature.  
     
     
         22 . The method of  claim 17 , wherein nitridizing comprises implanting nitrogen into tantalum.  
     
     
         23 . The method of  claim 17 , wherein nitridizing comprises exposing tantalum to a plasma containing nitrogen.  
     
     
         24 . The method of  claim 14 , further comprising depositing a barrier layer superjacent the gate insulator layer prior to depositing the layer of metal.  
     
     
         25 . A method of making complementary FETs, comprising: 
 forming a first doped region of a first conductivity type in a substrate;    forming a second doped region of a second conductivity type in the substrate;    forming a gate insulator layer over the first and second doped regions;    depositing a layer of metal over the gate insulator layer, the metal having a first work function;    patterning the metal layer to form gate electrodes;    modifying, after patterning, a portion of the metal layer such that the modified portion has a second work function; and    forming source/drain junctions aligned to the gate electrodes.    
     
     
         26 . The method of  claim 25 , further comprising depositing a barrier layer superjacent the gate insulator layer prior to depositing the layer of metal.