DRAM with vertical transistors and deep trench capacitors

Abstract

A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is desposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folder bitline DRAM, and a foler bitline DRAM with bordless bitline contact window.

What is claimed is:  
     
         1 . A DRAM cell with a vertical transistor and a deep trench capacitor, comprising: 
 a substrate;    a deep trench capacitor comprising an upper electrode, an insulating film and a storage electrode desposed in the substrate;    a gate of a vertical transistor disposed over the deep trench capacitor;    an ion doped layer disposed between the gate and the upper electrode of the capacitor;    an insulating layer disposed between the gate and the ion doped layer;    a gate insulating layer of the vertical transistor disposed on a sidewall of the gate;    a channel region located beside the gate insulating layer in the substrate;    a source disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and    a common drain disposed on the other side of the vertical channel region.    
     
     
         2 . The DRAM cell with a vertical transistor and a deep trench capacitor of  claim 1 , further comprising a shallow trench isolation at least disposed on one other sidewall of the ion doped layer.  
     
     
         3 . An open bitline DRAM with vertical transistors and deep trench capacitors, comprising: 
 a substrate;    a plurality of deep trench capacitors arranged with matrix in the substrate;    a plurality of wordlines paralleled with each other and disposed on the deep trench capacitors, wherein the wordlines substantially corresponding to the deep trench capacitors are functioned as gates, a lower portion of each gate disposed in the substrate;    an insulating layer disposed between each gate and each deep trench capacitor;    an ion doped layer disposed between each insulating layer and each deep trench capacitor;    a source disposed on a sidewall of each ion doped layer in the substrate;    a gate insulating layer disposed on a lower sidewall of each gate, wherein the source is located on one side of the gate insulating layer;    a common drain disposed between each two adjacent wordlines in the substrate, wherein the common drain is located on the other side of the gate insulating layer;    an active region disposed between each common drain and two lower gates beside the common drain;    a shallow trench isolation disposed outside the active region; and    a plurality of bitlines paralleled with each other, disposed on the common drains, and connected with the common drains.    
     
     
         4 . An open bitline DRAM with vertical transistors and deep trench capacitors, comprising: 
 a substrate;    a plurality of deep trench capacitors located in the substrate, wherein the deep trench capacitors belonging to different rows are arranged with a shift;    a plurality of zigzag wordlines paralleled with each other and disposed on the deep trench capacitors, wherein the wordlines substantially corresponding to the deep trench capacitors are functioned as gates, a lower portion of each gate disposed in the substrate;    an insulating layer disposed between each gate and each deep trench capacitor;    an ion doped layer disposed between each insulating layer and each deep trench capacitor;    a source disposed on a sidewall of each ion doped layer in the substrate;    a gate insulating layer disposed on a lower sidewall of each gate, wherein the source is located on one side of the gate insulating layer;    a common drain disposed between each two adjacent wordlines in the substrate, wherein the common drain is located on the other side of the gate insulating layer;    an active region disposed between each common drain and two lower gates beside the common drain;    a shallow trench isolation disposed outside the active region; and    a plurality of bitlines paralleling with each other disposed on the common drains and connected with the common drains.    
     
     
         5 . A folder bitline DRAM with vertical transistors and deep trench capacitors, comprising: 
 a substrate;    a plurality of wordlines disposed on the substrate;    a plurality of bitlines disposed over the wordlines and perpendicular to the wordlines;    each active region corresponding to the bitlines and comprising four adjacent wordlines, wherein the two outside wordlines are functioned as gates, the two inside wordlines are passing wordlines, wherein each two adjacent active regions corresponding to two adjacent bitlines are arranged with a shift;    a common drain disposed between the two gates belonging to the two outside wordlines;    a deep trench capacitor disposed below each gate;    an insulating layer disposed between each gate and each deep trench capacitor;    a contact window disposed between each passing wordline and each gate to connect the common drain and bitline;    an ion doped layer disposed between each insulating layer and each deep trench capacitor;    a source disposed on a sidewall of each ion doped layer in the substrate;    a gate insulating layer disposed on a sidewall of a lower portion of each gate, wherein the source is located on one side of the gate insulating layer; and    a shallow trench isolation disposed outside the active region.    
     
     
         6 . A folder bitline DRAM with vertical transistors, deep trench capacitors and borderless bitline contact windows, comprising: 
 a substrate;    a plurality of wordlines disposed on the substrate;    a plurality of deep trench capacitors disposed in the substrate, wherein the deep trench capacitors belonging to different rows are arranged with a shift, and two wordlines leap over each deep trench capacitor;    a plurality of bitlines disposed over the wordlines and perpendicular to the wordlines;    each active region corresponding to the bitlines and comprising two wordlines which leap different deep trench capacitors and functioned as gates, wherein each two adjacent active regions corresponding to two adjacent bitlines are arranged with a shift;    an insulating layer disposed between each gate and each deep trench capacitor;    a common drain disposed between the two gates belonging to the two wordlines which leap over different deep trench capacitors;    a deep trench capacitor disposed below each gate;    a contact window connected to the common drain and bitline;    an ion doped layer disposed between each insulating layer and each deep trench capacitor;    a source disposed on a sidewall of each ion doped layer in the substrate;    a gate insulating layer disposed on a sidewall of a portion of each gate, wherein the source is located on one side of the gate insulating layer; and    a shallow trench isolation disposed outside the active region.