Igfet with silicide contact on ultra-thin gate

Abstract

An IGFET with a silicide contact on an ultra-thin gate is disclosed. A method of forming the IGFET includes forming a gate over a semiconductor substrate, forming a source and a drain in the substrate, depositing a contact material over the gate, and reacting the contact material with the gate to form a silicide contact on the gate and consume at least one-half of the gate. By consuming such a large amount of the gate, a relatively thin gate can be converted into an ultra-thin gate with a thickness on the order of 100 to 200 angstroms. Preferably, the bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes a peak concentration of a dopant in the gate towards the substrate so that a heavy concentration of the dopant is pushed to the bottom surface of the gate without being pushed into the substrate. As exemplary materials, the contact material is a refractory metal such as titanium, the gate is polysilicon, and the dopant is arsenic.

What is claimed is:  
     
         1 . A method of forming an IGFET, comprising the steps of: 
 forming a gate over a semiconductor substrate;    forming a source and a drain in the substrate;    depositing a contact material over the gate; and    reacting the contact material with the gate to form a silicide contact on the gate and consume at least one-half of the gate.    
     
     
         2 . The method of  claim 1 , wherein reacting the contact material with the gate consumes at least three-quarters of the gate.  
     
     
         3 . The method of  claim 1 , wherein the silicide contact has a greater thickness than the gate after reacting the contact material with the gate.  
     
     
         4 . The method of  claim 1 , wherein the gate has a thickness of at most 500 angstroms after reacting the contact material with the gate.  
     
     
         5 . The method of  claim 1 , wherein the gate has a thickness of at most 200 angstroms after reacting the contact material with the gate.  
     
     
         6 . The method of  claim 1 , wherein the gate includes a peak concentration of a dopant before reacting the contact material with the gate, and reacting the contact material with the gate pushes the peak concentration of the dopant towards the substrate.  
     
     
         7 . The method of  claim 6 , wherein a bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes a substantial concentration of the dopant to the bottom surface of the gate.  
     
     
         8 . The method of  claim 1 , wherein the contact material is a refractory metal and the gate is polysilicon.  
     
     
         9 . An integrated circuit chip, including an IGFET fabricated in accordance with the method of  claim 1 .  
     
     
         10 . An electronic system including a microprocessor, a memory and a system bus, and further including an IGFET fabricated in accordance with the method of  claim 1 .  
     
     
         11 . A method of forming an IGFET, comprising the steps of: 
 forming a gate insulator on a semiconductor substrate;    forming a gate with a first thickness on the gate insulator;    implanting a dopant into the gate and the substrate;    forming a source and a drain in the substrate;    depositing a contact material over the gate; and    applying a thermal cycle to react the contact material with the gate and form a silicide contact on the gate, wherein reacting the contact material with the gate consumes at least one-half of the gate such that the gate has a second thickness, the first thickness is at least twice the second thickness, and the silicide contact has a greater thickness than the second thickness, and reacting the contact material with the gate pushes a peak concentration of the dopant in the gate towards the substrate.    
     
     
         12 . The method of  claim 11 , wherein reacting the contact material with the gate consumes at least three-quarters of the gate such that the first thickness is at least four times the second thickness, and the thickness of the silicide contact is at least twice the second thickness.  
     
     
         13 . The method of  claim 11 , wherein the second thickness is at most 200 angstroms.  
     
     
         14 . The method of  claim 11 , wherein reacting the contact material with the gate pushes the peak concentration of the dopant in the gate towards the substrate by way of a resultant interface between the silicide contact and the gate that advances beyond an original location of the peak concentration of the dopant in the gate.  
     
     
         15 . The method of  claim 14 , wherein a bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes a substantial concentration of the dopant to the bottom surface of the gate.  
     
     
         16 . The method of  claim 15 , wherein a lower region of the gate adjacent to the bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate consumes all of the gate except for the lower region of the gate and pushes a substantial concentration of the dopant into the lower region of the gate.  
     
     
         17 . The method of  claim 15 , wherein reacting the contact material with the gate pushes essentially none of the dopant through the gate insulator into the substrate.  
     
     
         18 . The method of  claim 11 , wherein the contact material is a refractory metal and the gate is polysilicon.  
     
     
         19 . The method of  claim 18 , wherein the refractory metal is titanium.  
     
     
         20 . The method of  claim 18 , wherein the dopant is arsenic.  
     
     
         21 . A method of forming an IGFET that includes producing an ultra-thin polysilicon gate, comprising the following steps in the sequence set forth: 
 providing a semiconductor substrate of first conductivity type;    forming a gate oxide on the substrate;    forming a polysilicon gate with a first thickness on the gate oxide;    implanting a dopant of second conductivity type into the polysilicon gate and the substrate;    forming a source and a drain of second conductivity type in the substrate, wherein the source and drain include the dopant; depositing a refractory metal over the polysilicon gate; and    applying a thermal cycle to react the refractory metal with the polysilicon gate and form a silicide contact on the polysilicon gate, wherein reacting the refractory metal with the polysilicon gate consumes at least one-half of the polysilicon gate such that the polysilicon gate has a second thickness of at most 500 angstroms, the first thickness is at least twice the second thickness, and the silicide contact has a greater thickness than the second thickness, and reacting the refractory metal with the polysilicon gate pushes a peak concentration of the dopant in the gate towards the substrate in snowplow fashion.    
     
     
         22 . The method of  claim 21 , wherein the second thickness is at most 200 angstroms.  
     
     
         23 . The method of  claim 21 , wherein reacting the refractory metal with the polysilicon gate pushes the peak concentration of the dopant in the polysilicon gate towards the substrate by way of a resultant interface between the silicide contact and the polysilicon gate that advances beyond an originzd location of the peak concentration of the dopant in the polysilicon gate.  
     
     
         24 . The method of  claim 21 , wherein the polysilicon gate includes a bottom surface adjacent to the gate oxide, a lower region of the polysilicon gate adjacent to the bottom surface of the polysilicon gate is essentially undoped before reacting the refractory metal with the polysilicon gate, and reacting the refractory metal with the polysilicon gate consumes all of the polysilicon gate except for the lower region of the polysilicon gate and pushes a heavy concentration of the dopant into all of the lower region of the polysilicon gate without pushing essentially any of the dopant through the gate oxide into the substrate.  
     
     
         25 . The method of  claim 21 , wherein the refractory metal is titanium.  
     
     
         26 . An IGFET, comprising: 
 a gate insulator on a semiconductor substrate;    a source and drain in the substrate;    a polysilicon gate on the gate insulator; and    a silicide contact on the polysilicon gate, wherein a thickness of the silicide contact is greater than a thickness of the polysilicon gate.    
     
     
         27 . The IGFET of  claim 26 , wherein the thickness of the polysilicon gate is at most 500 angstroms.  
     
     
         28 . The IGFET of  claim 26 , wherein the thickness of the polysilicon gate is at most 200 angstroms.  
     
     
         29 . The IGFET of  claim 26 , wherein the thickness of the silicide contact is at least twice the thickness of the polysilicon gate.  
     
     
         30 . The IGFET of  claim 26 , wherein the polysilicon gate includes a doping profile resulting from the silicide contact pushing a dopant into the polysilicon gate in snowplow fashion.