Nvram cell with planar control gate

Abstract

A nonvolatile memory cell utilizing planar control gates, which provides advantages of being compatible with self-aligned silicide processes and providing a planar surface for subsequent wiring processes. A substrate defines a first NVRAM region having large floating gate areas with smaller areas cutout to isolate individual memory cells, and a second CMOS Logic region. ONO is deposited on the floating gate areas, and a thick poly layer is deposited in a blanket manner over the first and second regions of the substrate. Resist shapes are patterned over the logic areas in the array where necessary according to a predetermined density algorithm. The poly layer is reactive ion etched, followed by a chemical mechanical polishing (CMP) operation. The final poly gate thickness is 200-220 nm in the CMOS logic areas and in the NVRAM control gate areas between floating gate regions, but only 100-120 nm for the NVRAM control gates over the floating gates. The control gate physical thickness is decoupled (isolated) from the standard logic by standard photoetching processes, and the final structure appears identical from a topological perspective to a standard CMOS structure.

Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:  
     
         1 . A method of fabricating mixed first and second type devices on a common substrate, which comprises: 
 a. providing a substrate having a first type device region thereon and a second type device region thereon, wherein the first type device region is thicker than the second type device region;    b. forming a continuous conductive laver over both the first type device region and the second type device region, wherein the conductive layer over the first type device region is to form first device gates, and the conductive layer over the second type device region is to form second device gates; and    c. planarizing the conductive layer such that the conductive layer forming the first device gates is planar with the conductive layer forming the second device gates, and the conductive layer forming the second device gates is thicker than the conductive layer forming the first device gates.    
     
     
         2 . A method as claimed in  claim 1 , wherein said step of providing comprises providing a substrate having a first NVRAM region thereon and a second CMOS region thereon, the step of forming comprises depositing a layer of polysilicon for the NVRAM control gates and the CMOS gates, and wherein following the planarizing step the upper surface of the resulting CMOS gates is planar with the upper surface of the NVRAM control gates, and the conductive layer forming the CMOS gates is thicker than the conductive layer forming the NVRAM gates over floating gate regions.  
     
     
         3 . A method as claimed in  claim 2 , wherein the planarizing step comprises reactive ion etching of the conductive layer through a mask, followed by chemical mechanical polishing of the conductive layer.  
     
     
         4 . A method as claimed in  claim 3 , wherein following the planarizing step, a metal layer is deposited, a silicide is formed on the planarized surface, followed by patterning to form discrete control gates.  
     
     
         5 . A method as claimed in  claim 3 , wherein following the planarizing step and patterning to form discrete control gates, a metal layer is deposited and a silicide is formed.  
     
     
         6 . A method as claimed in  claim 1 , wherein the planarizing step comprises reactive ion etching of the conductive layer through a mask, followed by chemical mechanical polishing of the conductive layer.  
     
     
         7 . A method as claimed in  claim 1 , wherein following the planarizing step, a metal layer is deposited, a silicide is formed on the planarized surface, followed by patterning to form discrete control gates.  
     
     
         8 . A method as claimed in  claim 1 , wherein following the planarizing step and patterning to form discrete control gates, a metal layer is deposited and a silicide is formed.  
     
     
         9 . A semiconductor device comprising: 
 a. a planar substrate;    b. a first multilayer device on the substrate having an upper conductive layer;    c. a second multilayer device on the substrate having a different number of layers than the first multilayer device and having an upper conductive layer; and    d. the upper conductive layers of the first and second multilayer devices have planarized coplanar top conductive surfaces.    
     
     
         10 . A semiconductor device as claimed in  claim 9 , wherein the upper conductive layer of the first multilayer device is thinner than the upper conductive layer of the second multilayer device.  
     
     
         11 . A semiconductor device as claimed in  claim 10 , wherein the first multilayer device comprises a control gate over a floating gate for an NVRAM memory cell, and the second multilayer device comprises a gate of an FET.  
     
     
         12 . A semiconductor device as claimed in  claim 11 , wherein the first multilayer device includes a layer of polysilicon for NVRAM control gates and the second multilayer device includes a layer of polysilicon for CMOS FET gates, and wherein following a planarizing operation the upper surface of the resulting CMOS gates is planar with the upper surface of the NVRAM control gates, and the upper conductive layer of the CMOS gates is thicker than the upper conductive layer of the NVRAM gates over floating gate regions.  
     
     
         13 . A semiconductor device as claimed in  claim 9 , wherein the first multilayer device comprises a control gate over a floating gate for an NVRAM memory cell, and the second multilayer device comprises a gate of an FET.  14 .  
     
     
         14 . A semiconductor device as claimed in  claim 9 , wherein the first multilayer device includes a layer of polysilicon for NVRAM control gates and the second multilayer device includes a layer of polysilicon for CMOS FET gates, and wherein following a planarizing operation the upper surface of the resulting CMOS gates is planar with the upper surface of the NVRAM control gates, and the upper conductive layer of CMOS gates is thicker than the upper conductive layer of NVRAM gates over floating gate regions.