Technique for producing small islands of silicon on insulator

Abstract

Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defmed on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

What is claimed is:  
     
         1 . A method for manufacturing a silicon on insulator substrate, comprising the steps of: 
 directionally etching a silicon substrate, to form a plurality of trenches between protruding silicon rows;    forming a silicon nitride cap on the silicon rows, extending partway down the sides of the trenches;    isotropically etching the trenches, to partially undercut the silicon rows; and    oxidizing the substrate, to fully undercut the silicon rows.    
     
     
         2 . The method of  claim 1 , wherein the silicon substrate has a {100} crystallographic orientation and the directional etch is in the <100> direction.  
     
     
         3 . The method of  claim 1 , wherein the directional etchant comprises a reactive ion etch.  
     
     
         4 . The method of  claim 1 , wherein the isotropic etchant comprises hydrofluoric acid.  
     
     
         5 . The method of  claim 1 , wherein the silicon rows have a width dimension of one micron or less.  
     
     
         6 . The method of  claim 1 , wherein the silicon rows have a width dimension of 0.25 microns or less.  
     
     
         7 . The method of  claim 1 , wherein the directional etch is approximately as deep as the width of the silicon rows and approximately as wide as the width of the silicon rows.  
     
     
         8 . The method of  claim 1 , wherein the oxidizing step comprises oxidizing the substrate in a wet oxidizing ambient at a temperature of approximately 900 to 1,100 degrees Celsius.  
     
     
         9 . The method of  claim 1 , and further comprising the step of: 
 defining a plurality of active areas on the silicon rows by local oxidation of silicon.    
     
     
         10 . The method of  claim 9 , and further comprising the step of: 
 forming a transistor on each of a plurality of the active areas.    
     
     
         11 . A silicon on insulator structure, comprising: 
 a plurality of silicon rows, having a width dimension of one micron or less, embedded in an oxidized substrate; and    a plurality of oxide rows between the silicon rows.    
     
     
         12 . The structure of  claim 11 , wherein the oxide rows have a width dimension of one micron or less.  
     
     
         13 . The structure of  claim 11 , wherein the silicon rows have a width dimension of 0.25 microns or less.  
     
     
         14 . The structure of  claim 11 , wherein the oxide rows have a width dimension of 0.25 microns or less.  
     
     
         15 . A plurality of active areas on a semiconductor substrate, comprising: 
 a plurality of isolated silicon active areas, having an area of one square micron or less, embedded in an oxidized substrate; and    a plurality of oxide rows between the silicon active areas in one direction.    
     
     
         16 . The structure of  claim 15 , and further comprising: 
 a plurality of transistors formed on each of a plurality of the silicon active areas.    
     
     
         17 . The structure of  claim 15 , wherein the oxide rows have a width dimension of one micron or less.  
     
     
         18 . The structure of  claim 15 , wherein the oxide rows have a width dimension of 0.25 microns or less.  
     
     
         19 . The structure of  claim 15 , wherein the area of the silicon active areas is 0.0625 square microns or less.  
     
     
         20 . The structure of  claim 15 , wherein the active areas are isolated using local oxidation of silicon.