Memory circuit with dynamic redundancy

Abstract

The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

What is claimed is:  
     
         1 . An integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and means for reversibly inhibiting the operation of a defective element and for maintaining the circuit operation by using the redundancy element.  
     
     
         2 . The circuit of  claim 1 , further including a means for definitively inhibiting the operation of a defective element.  
     
     
         3 . The circuit of  claim 1 , including several matrix networks of identical elements to be simultaneously addressed in a second direction, including, for each matrix network, a redundancy circuit for organizing the use of a redundancy element associated with this matrix network independently from the other matrix networks.  
     
     
         4 . A memory including at least one matrix network of cells and at least one redundancy element associated with a first direction, including at least one redundancy circuit of  claim 1  for reversibly modifying the addressing in the first direction to use the redundancy element in the presence of a defective memory cell in the matrix network.  
     
     
         5 . The memory of  claim 4 , including at least n+1 successive columns of cells, wherein the redundancy circuit includes as many logic units as the matrix network includes columns, n first units including a selector for routing an address conductor associated with the corresponding column, either to the memory cells associated with this column, or to the memory cells associated with the next column.  
     
     
         6 . The memory of  claim 5 , wherein each of the n first units further includes a fuse for definitively inhibiting the operation of a defective column.  
     
     
         7 . The memory of  claim 4 , including several matrix networks and, for each network, at least one redundancy element associated with a first direction and at least one redundancy circuit, each redundancy circuit being individually controllable.