Flip-flop circuit

Abstract

A low power, high performance flip-flop which does not require a full feedback path in the master stage includes a master stage driven by a data input, and an inverter. A slave stage includes a pass device for isolating the slave stage and the master stage, the slave stage having a feedback path for holding a data value passed to the slave stage.

What is claimed is:  
     
         1 . A flip flop, comprising: 
 a master stage having a pass gate and an inverter, the pass gate connected between an external data input and the inverter, the master stage driven directly by the data input; and    a slave stage having a feedback path for maintaining a data input value, the slave stage isolated from the master stage on a transition of a clock signal.    
     
     
         2 . The flip-flop of  claim 1 , wherein the slave stage further comprises a second pass gate connecting the slave stage to the master stage on the transition of the clock signal.  
     
     
         3 . The flip-flop of  claim 1 , wherein the feedback path comprises a pair of inverters connected back to back and a third pass gate in a loop.  
     
     
         4 . The flip-flop of  claim 3 , wherein the third pass gate is active when the second pass gate is inactive.  
     
     
         5 . The flip-flop of  claim 1 , wherein the feedback path comprises a pair of inverters connected back to back.  
     
     
         6 . The flip-flop of  claim 5 , wherein one of the inverters is a strong inverter and the other of the inverters is a weak inverter.  
     
     
         7 . The flip-flop of  claim 6 , wherein the strong inverter is approximate ly three times the size of the weak inverter.  
     
     
         8 . The flip-flop of  claim 1 , wherein the feedback path comprises a first strong inverter and a second weak inverter, the strong and weak inverters connected back to back.  
     
     
         9 . A flip-flop, comprising: 
 a master stage having a first transistor, a first inverter with its input connected to the first transistor, and a first half weak feedback path; and    a slave stage having a second transistor, a second inverter with its input connected to the second transistor, and a second half weak feedback path.    
     
     
         10 . The flip-flop of  claim 9 , wherein the first half weak feedback path comprises: 
 a third transistor connected between a logic one potential and a node defined between the first transistor and the first inverter, the output of the first inverter connected to the gate of the second transistor.    
     
     
         11 . The flip-flop of  claim 9 , wherein the second half weak feedback path comprises: 
 a fourth transistor connected between a logic one potential and a second node defined between the second transistor and the second inverter, the output of the second inverter connected to the gate of the fourth transistor.    
     
     
         12 . The flip-flop of  claim 11 , wherein the second half weak feedback path further comprises: 
 a fifth transistor and a sixth transistor connected in series between the second node and a logic zero potential, the fifth transistor on when the master stage pass transistor is on, and the sixth transistor having its gate connected to the output of the second inverter.    
     
     
         13 . A flip-flop, comprising: 
 a master stage having pass gate and an inverter connected to the pass gate, the pass gate connectable to an external data input; and    a slave stage having a second pass gate, a second inverter, and a feedback path between an output and an input of the second inverter, the feedback path for storing a previous data input value passed to the slave stage.    
     
     
         14 . The flip-flop of  claim 13 , wherein the slave stage is connected to the master stage on a rising edge of a clock signal.  
     
     
         15 . A flip-flop, comprising: 
 a master stage having a pass gate connectable to an external data input and an inverter connected to the pass gate;    a slave stage having a second pass gate for connecting to the master stage, and a feedback path having a strong inverter and a weak inverter.    
     
     
         16 . The flip-flop of  claim 15 , wherein the slave stage is connected with the master stage upon a transition of a clock signal from a first state to a second state, and the slave stage is isolated from the master stage on a transition of the clock signal from the second state to the first state.  
     
     
         17 . The flip-flop of  claim 15 , wherein the weak inverter is approximately one third the size of the strong inverter.  
     
     
         18 . A flip-flop, comprising: 
 a master stage having a pass transistor, an inverter, and a first half feedback path between the output and input of the inverter;    a slave stage having a pass transistor, an inverter, and a second half feedback path between the output and input of the inverter, the slave stage connectable to the master stage through the slave stage pass transistor.    
     
     
         19 . The flip-flop of  claim 18 , wherein the first half feedback path comprises: 
 a feedback transistor connected between a logic one potential and a node defined between the master stage pass transistor and the master stage inverter, the output of the master stage inverter connected to the gate of the slave stage pass transistor.    
     
     
         20 . The flip-flop of  claim 18 , wherein the second half feedback path comprises: 
 a feedback transistor connected between a logic one potential and a node defined between the slave stage pass transistor and the slave stage inverter, the output of the slave stage inverter connected to the gate of the transistor.    
     
     
         21 . The flip-flop of  claim 18 , wherein the second half feedback path further comprises: 
 a pull down transistor path between the node and a logic zero potential.    
     
     
         22 . The flip-flop of  claim 21 , wherein the pull down transistor path comprises: 
 a second pass transistor and a pull down transistor connected in series between the second node and the logic zero potential, the second pass transistor on when the master stage pass transistor is on, and the pull down transistor having its gate connected to the output of the second inverter.    
     
     
         23 . The flip-flop of  claim 18 , wherein the first half feedback path comprises: 
 a feedback transistor connected between a logic zero potential and a node defined between the master stage pass transistor and the master stage inverter, the output of the master stage inverter connected to the gate of the slave stage pass transistor.    
     
     
         24 . The flip-flop of  claim 18 , wherein the second half feedback path comprises: 
 a feedback transistor connected between a logic zero potential and a node defined between the slave stage pass transistor and the slave stage inverter, the output of the slave stage inverter connected to the gate of the transistor.    
     
     
         25 . A flip-flop, comprising: 
 a master stage comprising: 
 a master stage pass transistor connectable to a data input;  
 a master stage inverter connected to the master stage pass transistor; and  
 a half feedback path comprising a pull up transistor, the half feedback path connected between the input and output of the master stage inverter; and 
 a slave stage connected to the master stage, comprising:  
 a slave stage pass transistor connected to the output of the master stage inverter;  
 a slave stage inverter connected to the slave stage pass transistor;  
 a slave stage half feedback path comprising a pull up transistor, the slave stage half feedback path connected between the input and output of the slave stage inverter; and  
 a pull down transistor connected between the input and output of the slave stage inverter;  
 wherein each pull up transistor restores a logic one signal to the data, and wherein the pull down transistor restores a logic zero signal to the data in the slave stage.  
 
   
     
     
         26 . A method, comprising: 
 supplying a data input to a first network having a pass device and an inverter;    isolating the first network from a second network until a triggering event;    connecting the first network to the second network to pass a new data value to the second network; and    holding a passed data value in the second network using a feedback path.    
     
     
         27 . The method of  claim 26 , wherein holding the passed data value comprises latching the data value.  
     
     
         28 . The method of  claim 27 , wherein latching the data value comprises latching the data value in a latch having a strong inverter and a weak inverter connected back to back.  
     
     
         29 . The method of  claim 26 , wherein connecting the first network to the second network is accomplished with a pass transistor.  
     
     
         30 . The method of  claim 29 , and further comprising: 
 supplying a half weak feedback path for restoring a passed logic data value to a full logic data value.    
     
     
         31 . An integrated circuit, comprising: 
 a first input connection for receiving a clock signal;    a second input connection for receiving an input data signal; and    a flip-flop circuit coupled to receive the clock signal and the input data signal, the flip-flop comprising: 
 a master stage having a pass gate and an inverter, the pass gate connected between an external data input and the inverter, the master stage driven directly by the data input; and  
 a slave stage having a feedback path for maintaining a data input value, the slave stage isolated from the master stage when a clock signal is in a first state, and connectable to the master stage inverter on a transition of the clock signal to a second state.