Method and circuit for reducing power and/or current consumption

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a device input signal. The apparatus may be configured to perform a predefined function in response to the device input signal during normal operation. The second circuit may be configured to determine when the device input signal is invalid according to a predetermined parameter. The second circuit may be configured to generate a function control signal in response to the predetermined parameter. The function control signal may be configured to direct the apparatus to perform a second predetermined function. The second predetermined function may be different than the first predetermined function.

1 . A semiconductor device comprising: 
 means for receiving a device input signal wherein said semiconductor device is configured to perform a predefined function responsive to said device input signal during normal operation of said semiconductor device; and    means for (i) determining when said device input signal is invalid according to a predetermined parameter and (ii) generating in response thereto a function control signal configured to direct said semiconductor device to perform a second predetermined function, wherein said second predetermined function is different than said first predetermined function.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein said predetermined parameter comprises a preselected jitter value associated with said device input signal.  
     
     
         3 . The semiconductor device according to  claim 1 , further comprising: 
 a phase-locked loop (PLL) circuit having an input terminal for receiving said device input signal and an output terminal for generating a PLL output signal wherein said device input signal comprises said PLL output signal.    
     
     
         4 . The semiconductor device according to  claim 3 , wherein said minimum threshold frequency comprises a voltage on a control node associated with a voltage controlled oscillator portion of said PLL.  
     
     
         5 . An apparatus comprising: 
 a first circuit configured to receive a device input signal, wherein, said apparatus is configured to perform a predefined function in response to said device input signal during normal operation; and    a second circuit configured to generate a function control signal when said device input signal is invalid according to a predetermined parameter, wherein said second circuit is configured to direct said apparatus to perform an second predetermined function, wherein said second predetermined function is different than said first predetermined function.    
     
     
         6 . The apparatus according to  claim 5 , wherein said predetermined parameter comprises a preselected jitter value associated with said device input signal.  
     
     
         7 . The apparatus according to  claim 5 , further comprising: 
 a phase-locked loop (PLL) circuit having (i) an input terminal configured to receive said device input signal and (ii) an output terminal configured to generate said device input signal.    
     
     
         8 . The apparatus according to  claim 7 , wherein said minimum threshold frequency comprises a voltage on a control node associated with a voltage controlled oscillator portion of said PLL.