Semiconductor device including misfet having post-oxide films having at least two kinds of thickness and method of manufacturing the same

Abstract

Disclosed is a semiconductor device in which first and second MISFETs are formed, each of the first and second MISFETs including a source region, a drain region, a gate insulating film, a gate electrode and a covering insulating film. The source region and the drain regions are formed apart from each other within a semiconductor substrate. The gate insulating film is formed on the surface of the semiconductor substrate and positioned between the source region and the drain region, and the gate electrode is formed on the gate insulating film. The covering insulating film is formed to cover the side surface of the gate electrode, the gate insulating film and a part of the source region or the drain region. The first and second MISFETs differ from each other in the thickness of a first region of the covering insulating film positioned to cover the source region or the drain region.

What is claimed is:  
     
         1 . A semiconductor device including first and second MISFETs, each of said first and second MISFETs comprising: 
 a semiconductor substrate common to the first and second MISFETs;    a source region formed in said semiconductor substrate;    a drain region formed in the semiconductor substrate apart from said source region;    a gate insulating film provided on the surface of the semiconductor substrate and positioned between the source region and the drain region;    a gate electrode provided on said gate insulating film; and    a covering insulating film having a first region arranged on the source region and the drain region and a second region arranged on the side surfaces of the gate electrode and the gate insulating film, said first region in said first MISFET differing in thickness from said first region in said second MISFET.    
     
     
         2 . A semiconductor device including first and second MISFETs, each of said first and second MISFETs comprising: 
 a semiconductor substrate common to the first and second MISFETs;    a source region formed in said semiconductor substrate;    a drain region formed in the semiconductor substrate apart from said source region;    a gate insulating film provided on the surface of the semiconductor substrate and positioned between the source region and the drain region;    a gate electrode provided on said gate insulating film; and    a covering insulating film having a first region arranged on the source region and the drain region and a second region arranged on the side surfaces of the gate electrode and the gate insulating film, said first and second region in said first MISFET differing in thickness from said first and second region in said second MISFET.    
     
     
         3 . The semiconductor device according to  claim 1 , wherein said covering insulating film is an insulating film selected from the group consisting of a semiconductor oxide film, a semiconductor nitride film and a semiconductor oxynitride film.  
     
     
         4 . The semiconductor device according to  claim 1 , further comprising a CVD insulating film formed by a CVD method, said CVD insulating film covering the periphery of said covering film.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein said gate electrode has a side surface in contact with said covering insulating film and a bottom surface in contact with said gate insulating film, the corner portion of said gate electrode ranging between said side surface and said gate bottom surface being rounded.  
     
     
         6 . The semiconductor device according to  claim 1 , wherein said first and second regions of said covering insulating film are substantially equal to each other in the thickness in each of said first and second MISFETs.  
     
     
         7 . The semiconductor device according to  claim 1 , wherein said gate insulating film has a first thickness and a second thickness larger than said first thickness, said covering insulating film has a third thickness and a fourth thickness larger than third thickness, said first MISFET includes the gate insulating film having said first thickness and the covering insulating film having said third thickness, and said second MISFET includes the gate insulating film having said second thickness and the covering insulating film having said fourth thickness.  
     
     
         8 . The semiconductor device according to  claim 7 , wherein said first MISFET constitutes a logic circuit or an SRAM circuit, and said second MISFET constitutes a DRAM circuit or an analog circuit.  
     
     
         9 . A method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of: 
 providing gate insulating films of said first and second MISFETs on a semiconductor substrate;    providing gate electrodes on said gate insulating films;    covering the gate electrodes of said first and second MISFETs with an insulating material film, said material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said first and second MISFETs;    decreasing the thickness of said insulating material film by etching in a region corresponding to said first region of said covering insulating film in said first MISFET; and    forming after said etching step a source region and a drain region in the surface region of said semiconductor substrate by ion implantation through said first region of said covering insulating film with the gate electrode used as a mask in said first and second MISFETs.    
     
     
         10 . The method of manufacturing a semiconductor device according to  claim 9 , wherein said etching is applied to only said covering insulating film of said first MISFET with the covering insulating film of said second MISFET covered with a resist mask.  
     
     
         11 . The method of manufacturing a semiconductor device according to  claim 9 , further comprising the step of forming a CVD insulating film by a CVD method, said CVD insulating film covering the periphery of said covering insulating film.  
     
     
         12 . A method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of: 
 providing gate insulating films of said first and second MISFETs on a semiconductor substrate;    providing gate electrodes on said gate insulating films;    covering the gate electrode of said first and second MISFETs with a first insulating material film, said first insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said second MISFET;    removing said first insulating material film from said first MISFET;    covering, after removal of said first insulating film, the gate electrode of said first MISFET with a second insulating material film, said second insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said first MISFET; and    forming after the gate electrode of said first MISFET is covered with said second insulating material film, a source region and a drain region in the surface region of said semiconductor substrate by ion implantation through said first region of said covering insulating film with the gate electrode used as a mask in said first and second MISFETs.    
     
     
         13 . The method of manufacturing a semi conductor device according to  claim 12 , wherein said step of removing said first insulating material film is performed by etching only said first insulating film of said first MISFET, with the first insulating material film of said second MISFET covered with a resist mask.  
     
     
         14 . The method of manufacturing a semiconductor device according to  claim 12 , further comprising the step of forming a CVD insulating film by a CVD method, said CVD insulating film covering the periphery of said covering insulating film.  
     
     
         15 . A method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of: 
 providing gate insulating films of said first and second MISFETs on a semiconductor substrate;    providing gate electrodes on said gate insulating films;    implanting ions selected from the group consisting of ions that permit changing the oxidizing rate, ions that permit changing the nitriding rate and ions that permit changing the oxynitriding rate into regions in which said first MISFET is to be formed;    covering the gate electrodes of said first and second MISFETs with an insulating material film, said insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said first and second MISFETs; and    forming, after the gate electrodes of said first and second MISFETs are covered with said insulating material film, a source region and a drain region in the surface region of said semiconductor substrate by ion implantation through said first region of said covering insulating film with the gate electrode used as a mask in said first and second MISFETs;    wherein, in the case of implanting ions that permit changing the oxidizing rate, said covering insulating film is a semiconductor oxide film; in the case of implanting ions that permit changing the nitriding rate, said covering insulating film is a semiconductor nitride film; and in the case of implanting ions that permit changing the oxynitriding rate, said covering insulating film is a semiconductor oxynitride film.    
     
     
         16 . The method of manufacturing a semiconductor device according to  claim 15 , further comprising the step of forming a CVD insulating film by a CVD method, said CVD insulating film covering the periphery of said covering insulating film.  
     
     
         17 . The method of manufacturing a semiconductor device according to  claim 15 , wherein said ion implantation is performed by inclining the running direction of the ions relative to said semiconductor substrate so as to allow said covering insulating film of said first MISFET to have said first region and said region differing from each other in thickness.  
     
     
         18 . The method of manufacturing a semiconductor device according to  claim 15 , wherein said ion implantation is performed by inclining the running direction of the ions relative to said semiconductor substrate so as to allow said covering insulating film of said first MISFET to have said second region having a uniform thickness.  
     
     
         19 . The method of manufacturing a semiconductor device according to  claim 15 , wherein said ion implantation is performed from all directions of the side surface of said gate electrode of said first MISFET so as to allow said covering insulating film of the first MISFET to have said second region having a uniform thickness in every direction.  
     
     
         20 . A method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of: 
 providing gate insulating films of said first and second MISFETs on a semiconductor substrate;    providing an electrode material film providing the basis of a gate electrode on said gate insulating films;    etching said electrode material film in said first MISFET so as to form said gate electrode;    covering, after said etching step, the gate electrode in said first MISFET and said electrode material film in said second MISFET with a first insulating material film, said first insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in said first MISFET;    etching said first insulating film and said electrode material film in said second MISFET so as to form said gate electrode;    removing the first insulating material film in said second MISFET after said etching step;    covering the gate electrode with a second insulating material film in said second MISFET after removal of said first insulating material film, said second insulating material film providing the basis of a covering insulating film having a first region arranged on said semiconductor substrate and second region arranged on the side surfaces of the gate electrode and the gate insulating film in said second MISFET; and    forming, after the gate electrode of said second MISFET is covered with said second insulating material film, a source region and a drain region in the surface region of said semiconductor substrate by ion implantation through said first region of said covering insulating film with the gate electrode used as a mask in said first and second MISFETs.    
     
     
         21 . The method of manufacturing a semiconductor device according to  claim 20 , further comprising the step of forming a CVD insulating film by a CVD method, said CVD insulating film covering the periphery of said covering insulating film.