Improving field leakage by using a thin layer of nitride deposited by chemical vapor deposition

Abstract

A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

What is claimed is:  
     
         1 . A method of manufacturing integrated circuits comprising the steps of: 
 creating source and drain regions for a first transistor;    creating source and drain regions for a second transistor;    creating a field oxide between the first transistor and the second transistor; and    applying a layer of nitride above the polysilicon gate and field oxide layers.    
     
     
         2 . The method of  claim 1  further comprising the steps of: 
 depositing a polysilicon region above the field oxide layer prior to depositing the nitride layer; and  
 applying a layer of dielectric material above the nitride layer.  
 
     
     
         3 . The method of  claim 1  further comprising the step of: 
 depositing the nitride layer using chemical vapor deposition.  
 
     
     
         4 . The method of  claim 1  wherein the source and drain regions of the first and second transistors are n-type implant regions.  
     
     
         5 . The method of  claim 1 , wherein the thickness of the nitride layer is between about 100 Å and about 250 Å.  
     
     
         6 . The method of  claim 5  wherein the thickness of the nitride layer is between about 150 Å and about 200 Å.  
     
     
         7 . The method of  claim 5  wherein the thickness of the nitride layer is about 180 Å.  
     
     
         8 . A semiconductor device comprising: 
 a p-type substrate;    a first transistor including n-type source and drain regions provided in the substrate;    a second transistor including n-type source and drain regions provided in the substrate;    a field oxide region provided in the substrate between the first transistor and the second transistor;    a nitride layer provided above at least a portion of the field oxide region;    
     
     
         9 . The semiconductor device of  claim 8  further comprising: 
 a polysilicon region overlying the field oxide region and provided beneath the nitride layer.  
 
     
     
         10 . The semiconductor device of  claim 8  wherein the nitride layer is a dielectric nitride layer.  
     
     
         11 . The semiconductor device of  claim 10  wherein the nitride layer is silicon nitride.  
     
     
         12 . A semiconductor apparatus comprising: 
 a field oxide region provided in a substrate between a first transistor and a second transistor; and    means for increasing transistor voltage threshold, comprising depositing a layer of nitride over the field oxide layer.    
     
     
         13 . A semiconductor apparatus comprising: 
 a field oxide region provided in a substrate between a first transistor and a second transistor; and    means for decreasing the diffusion of cations into the field oxide layer, comprising a layer of nitride over the field oxide layer.    
     
     
         14 . The apparatus of  claim 12 , wherein the cations are at least one of hydrogen and sodium ions.