Semiconductor device and manufacturing method thereof

Abstract

A Si 3 N 4 film and a side wall are provided on an electrode to obtain a Cs capacitor capable of enlarging an area of a memory cell contact of a DRAM, and a hole if formed penetrating an inter-layer film by a selective etching process. The Si 3 N 4 film and the side wall are left without being etched, and an area of the hole through which a substrate is exposed, is smaller than an upper portion area of the hole.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate;    a gate electrode formed on said semiconductor substrate and extending in a first direction;    a first protection layer formed along a side wall of said gate electrode as well as on said gate electrode, and exhibiting an insulating property;    an inter-layer insulating layer formed over said semiconductor substrate including said first protection layer, having an opening portion extending to said first protection layer and said semiconductor substrate as well, and exhibiting a selectivity for said first protection layer when in an etching process; and    a capacitor formed inwardly of said opening portion.    
     
     
         2 . A semiconductor device according to  claim 1 , wherein said first protection layer is a nitride layer, and 
 said inter-layer insulating layer is an oxide layer.    
     
     
         3 . A semiconductor device according to  claim 1  or  2 , wherein said capacitor is constructed of a first conductive layer connected to said semiconductor substrate and having a rugged surface; 
 a capacitor insulating film formed on said first conductive layer; and  
 a second conductive layer formed on said capacitor insulating film.  
 
     
     
         4 . A semiconductor device according to any one of claims  1  through  3 , wherein said inter-layer insulating layer is constructed of a first insulating layer and a second insulating layer formed on said first insulating layer, 
 said inter-layer insulating layer contains a bit line provided between said first insulating layer and said second insulating layer and extending in a direction substantially orthogonal to the first direction, and a second protection layer provided on said bit line and along a side wall of said bit line and exhibiting a selectivity with respect to said inter-layer insulating layer when in an etching process and also an insulating property, and  
 said opening portion extends to said second protection layer.  
 
     
     
         5 . A method of manufacturing a semiconductor device, comprising: 
 a step of forming a gate insulating film and a gate electrode on a semiconductor substrate;    a step of forming a protection layer exhibiting an insulating property on an upper portion of said gate electrode and along a side wall thereof;    a step of forming an inter-layer insulating layer on said semiconductor substrate including said protection layer;    a step of forming an opening portion extending to said protection layer and to said semiconductor substrate by selectively etching said inter-layer insulting layer; and    a step of forming a capacitor inwardly of said opening portion.    
     
     
         6 . A method of manufacturing a semiconductor device, comprising: 
 a step of forming a gate insulating film and a gate electrode extending in a first direction on a semiconductor substrate;    a step of forming a first protection layer exhibiting an insulating property on an upper portion of said gate electrode and along a side wall thereof;    a step of forming a first inter-layer insulating layer having a selectivity when in an etching process with respect to said first protection layer on said semiconductor substrate including said first protection layer;    a step of forming a bit line extending in a second direction substantially orthogonal to the first direction on said first inter-layer insulating layer;    a step of forming a second protection layer having the selectivity when in the etching process with respect to said first inter-layer insulating layer an upper portion of said bit line and along a side wall thereof;    a step of forming a second inter-layer insulating layer having the selectivity and an insulating property with respect to said first and second protection layers on sid first inter-layer insulating layer including said second protection layer;    a step of forming an opening portion extending to said first and second protection layers and said semiconductor substrate by selectively etching said first and second inter-layer insulating layers; and    a step of forming a capacitor inwardly of said opening portion.    
     
     
         7 . A method of manufacturing a semiconductor device according to  claim 5  or  6 , wherein said capacitor forming step comprises: 
 a step of forming a conductive layer inwardly of said opening portion and forming a first conductive layer having a ruggedness by adhering conductive particles onto said conductive layer;  
 a step of forming capacitor insulating film on said first conductive layer; and  
 a step of forming a second conductive film on said capacitor insulating film.