Serial access memory and data write/read method

Abstract

An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC 11 to MCm 1 connected with a word line WL 1 to the read registers Rreg- 1 to Rreg-m all at once, the data stored in the memory cells MC 12 to MCm 2 connected with a word line WL 2 is transferred to the write registers Wreg- 1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD,/WD, an input/output means 122, and the second read data buses RD 2, /RD 2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD 2, /RD 2.

What is claimed is:  
     
         1 . A data write/read method applicable to a serial access memory of the class wherein there are provided: 
 a plurality of memory cells arranged at each of intersections made by a plurality of word lines and a plurality of bit lines,    the first register having a capacity capable of storing one word data stored in said plural memory cells connected with each of said plural word lines, and    the second register having a capacity capable of storing one word data stored in said plural memory cells connected with each of said plural word lines,    said data write/read method comprising: 
 the first write step of storing the first input serial data of one word in said first register; and  
 the second write step of transferring the one word data stored in said first register in said first write step, to said plural memory cells connected with each of a plurality of first selected word lines selected from said plural word lines.  
   
     
     
         2 . A method as claimed in    claim 1    further comprising: 
 the third write step of storing the second input serial data of one word in said first register, said second input serial data being obtained by inverting the logical level of each bit of said first input serial data; and  
 the fourth write step of transferring the one word data stored in said first register in said third write step, to said plural memory cells connected with each of a plurality of the second selected word lines selected from said plural word lines.  
 
     
     
         3 . A method as claimed in    claim 2    wherein there are included: 
 the first read step of selecting one first selected word line from said plural first selected word lines, and transferring the data stored in a plurality of memory cells connected with said one first selected word line to said second register;  
 the second read step of selecting one second selected word line from said plural second selected word lines, and transferring the data stored in a plurality of memory cells connected with said one second selected word line to said first register; and  
 the third read step of serially reading out the data transferred to said second register in said first read step and serially reading out the data transferred to the first register in said second read step.  
 
     
     
         4 . A method as claimed in    claim 1    further comprising: 
 the third write step of transferring said one word data stored in said first register, through a logic level inversion and transfer means for inverting the logical level on the basis of bit by bit, to a plurality of memory cells connected with each of said plural second selected word lines selected from said plural word lines.  
 
     
     
         5 . A method as claimed in    claim 4    wherein there are included: 
 the first read step of selecting one first selected word line from said plural first selected word lines, and transferring the data stored in a plurality of memory cells connected with said one first selected word line to said second register;  
 the second read step of selecting one second selected word line from said plural second selected word lines, and transferring the storage data of a plurality of memory cells connected with said one second selected word line to said first register; and  
 the third read step of serially reading out the data transferred to said second register in said first read step and serially reading out the data transferred to the first register in said second read step.  
 
     
     
         6 . A method as claimed in    claim 5    wherein there is included: 
 the data comparison step of comparing the data serially read out from said first register with the data serially read out from said second register on the bit by bit basis.  
 
     
     
         7 . A method as claimed in    claim 6    wherein there is included: 
 the logical level inversion step of inverting the logical level of each bit which is serially read out from said first register before said data comparison step.  
 
     
     
         8 . A method as claimed in    claim 1    further comprising: 
 the first read step of selecting two word lines from said plural first selected word lines, transferring the storage data of a plurality of memory cells connected with one of said selected two word lines to said second register, and transferring the storage data of a plurality of memory cells connected with the other word line of said selected two word lines to said first register; and  
 the second read step of serially reading out the data transferred to said first register in said first read step and serially reading out the data transferred to said second register in said first read step.  
 
     
     
         9 . A method as claimed in    claim 8    wherein there is included: 
 the data comparison step of comparing the data serially read out from said first register with the data serially read out from said second register on the bit by bit basis.  
 
     
     
         10 . A method as claimed in    claim 9    wherein there is included: 
 the logical level inversion step of inverting the logical level of each bit of the data which is serially read out from said first register prior said data comparison step.  
 
     
     
         11 . A serial access memory comprising: 
 a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines;    a register having a capacity capable of storing one word data stored in said plural memory cells connected with each of said plural word lines and storing an input serial data of one word; and    a register data transfer means transferring said one word data stored in said register as it is or after inverting the logical level of each bit thereof to a plurality of memory cells connected with one selected word line selected from said plural word lines.    
     
     
         12 . A serial access memory comprising: 
 a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines;    a register having m pieces of data storage region (m: positive integer) and transferring the data stored in said m pieces of data storage region to each of m pieces of memory cell connected with one selected word line selected from said plural word lines;    m pieces of bus data transfer means being assigned to each of said m pieces of data storage region and transferring the data transmitted to said data buses to each of said data storage region; and    a bus data transfer instruction means selecting in sequence said m pieces of bus data transfer means one by one or a plurality of them each, and instructing said selected bus data transfer means to transfer the data transmitted to said data buses to said data storage regions in sequence.    
     
     
         13 . A serial access memory comprising: 
 a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines;    a register having m pieces of data storage region and transferring the data stored in said m pieces of data storage region to each of m pieces of memory cell connected with one selected word line selected from said plural word lines;    an address means for asserting m pieces of address signal in sequence and outputting asserted address signals; and    m pieces of data transfer means being assigned to each of said m pieces of data storage region and having the function of transferring said m pieces of address signal to each of said data storage regions as the data, and also having the function of transferring the input serial data transmitted to said data buses, to each of said m pieces of data storage region with said m pieces of address signals.