Analog storage for a CMOS array

Abstract

The image sensor comprises an analog memory array integrated on a die with a CMOS sensor array and coupled to the sensor array for receiving light intensity signals from the sensor array. The sensor array may comprise light sensitive pixels arranged in rows and columns equal in number or greater than the number of memory cells in the memory array which are also arranged in rows and columns. The memory cells may be grouped into one or more distinct memory arrays. The image sensor operates in a rolling shutter mode which closely approximates electronic frame capture since the transfer process can be made sufficiently fast. This CMOS image sensor is particularly advantageous since it can be produced without requiring a special manufacturing process and still maintains a high performance level. Certain features of the image sensor along with the optical isolation of the memory array result in longer hold times in the memory cells by reducing the effects of light piping, optically enhanced sub-threshold current, and photo charge in the substrate. Structural variations in the sensor and the memory arrays may be compensated by double sampling the data from the sensor array.

What is claimed is:  
     
         1 . An image sensor comprising: 
 a CMOS sensor array integrated on a die; and    an analog memory array integrated on the die and coupled to the sensor array for receiving light intensity signals from the sensor array.    
     
     
         2 . An image sensor as claimed in    claim 1    wherein the sensor array comprises a number N of light sensitive pixels arranged in rows and columns.  
     
     
         3 . An image sensor as claimed in    claim 2    wherein the memory array comprises a number M of memory cells arranged in rows and columns.  
     
     
         4 . An image sensor as claimed in    claim 3    wherein the number N of pixels is equal to the number M of memory cells.  
     
     
         5 . An image sensor as claimed in    claim 3    wherein the number N of pixels is greater than the number M of memory cells.  
     
     
         6 . An image sensor as claimed in    claim 1    wherein the memory array is physically spaced from the sensor array at a distance greater than the recombination length of electron-hole pairs between the arrays.  
     
     
         7 . An image sensor as claimed in    claim 6    wherein the distance between the memory array and the sensor array is greater than approximately 50 microns.  
     
     
         8 . An image sensor as claimed in    claim 6    wherein the die includes a doped trench between the memory array and the sensor array adapted to be biased to collect free carriers.  
     
     
         9 . An image sensor as claimed in    claim 6    wherein the memory array is optically isolated.  
     
     
         10 . An image sensor as claimed in    claim 1    which further comprises conductive lines for coupling the sensor array and the memory array.  
     
     
         11 . An image sensor as claimed in    claim 10    wherein the conductive lines follow a winding path.  
     
     
         12 . An image sensor as claimed in    claim 10    wherein the die between the sensor array and the memory array includes an arrangement of vertical conductive column structures.  
     
     
         13 . An image sensor as claimed in    claim 12    wherein the conductive lines follow a winding path through the column structures.  
     
     
         14 . An image sensor as claimed in    claim 2    wherein the memory array comprises a number M of memory cells arranged in rows and columns and grouped into at least two distinct memory arrays.  
     
     
         15 . An image sensor as claimed in    claim 14    wherein the number N of pixels is equal to the number M of memory cells.  
     
     
         16 . An image sensor as claimed in    claim 4    wherein: 
 each column of pixels is coupled through a column data line by an access transistor to a column amplifier; and  
 the column amplifier is coupled to each memory cell in the column through a memory data line.  
 
     
     
         17 . An image sensor as claimed in    claim 16    wherein each memory cell comprises capacitor means for storing a charge and an access transistor coupled between the capacitor means and the memory data line.  
     
     
         18 . An image sensor as claimed in    claim 17    which further comprises switch means couple between an intermediate voltage source and each of the memory column data lines and adapted to apply an intermediate voltage to the memory data lines when signals are not being transferred to or from the memory cells.  
     
     
         19 . An image sensor as claimed in    claim 16    wherein the column amplifier is adapted to apply a signal to the capacitor means in the memory cell which is the difference between the pixel reset signal and the pixel light intensity signal.  
     
     
         20 . An image sensor as claimed in    claim 16    wherein column amplifier is adapted to apply the pixel light intensity signal followed by the pixel reset signal to the capacitor means in the memory cell.