PD-SOI substrate with suppressed floating body effect and method for its fabrication

Abstract

A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
         1 . A SOI structure comprising: 
 a silicon/germanium layer formed between a first silicon layer and a second silicon layer, said silicon/germanium layer being in contact with said first and second silicon layers; and    an oxide layer formed over a semiconductor substrate, said oxide layer being in contact with said second silicon layer.    
     
     
         2 . The SOI structure of    claim 1   , wherein said silicon/germanium layer is an epitaxial silicon/germanium layer.  
     
     
         3 . The SOI structure of    claim 1   , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.  
     
     
         4 . The SOI structure of    claim 1   , wherein said silicon/germanium layer is approximately 200 Angstroms thick.  
     
     
         5 . The SOI structure of    claim 1   , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.  
     
     
         6 . The SOI structure of    claim 1   , wherein said silicon/germanium layer comprises approximately 5% germanium.  
     
     
         7 . The SOI structure of    claim 1   , wherein said first silicon layer is an epitaxial silicon layer.  
     
     
         8 . The SOI structure of    claim 7   , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.  
     
     
         9 . The SOI structure of    claim 7   , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick.  
     
     
         10 . The SOI structure of    claim 1   , wherein said second silicon layer is an epitaxial silicon layer.  
     
     
         11 . The SOI structure of    claim 10   , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         12 . The SOI structure of    claim 10   , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick.  
     
     
         13 . The SOI structure of    claim 1   , wherein said oxide layer is approximately 1 micron thick.  
     
     
         14 . The SOI structure of    claim 1   , wherein said semiconductor substrate is a silicon substrate.  
     
     
         15 . The SOI structure of    claim 1   , wherein said semiconductor substrate is a silicon-on-saphire substrate.  
     
     
         16 . The SOI structure of    claim 1    wherein said semiconductor substrate is a germanium substrate.  
     
     
         17 . The SOI structure of    claim 1   , wherein said semiconductor substrate is a gallium-arsenide substrate.  
     
     
         18 . The SOI structure of    claim 1   , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.  
     
     
         19 . The SOI structure of    claim 16   , wherein said oxide layer is formed of silicon dioxide.  
     
     
         20 . A method for forming a SOI structure, comprising the steps of: 
 forming an oxide layer over a first semiconductor substrate;    forming a first silicon layer over a second silicon substrate;    forming a silicon/germanium layer over said first silicon layer;    forming a second silicon layer over said silicon/germanium layer; and    bonding said second silicon layer to said oxide layer.    
     
     
         21 . The method of    claim 20   , wherein said silicon/germanium layer is grown epitaxially over said first silicon layer.  
     
     
         22 . The method of    claim 20   , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.  
     
     
         23 . The method of    claim 20   , wherein said silicon/germanium layer is approximately 200 Angstroms thick.  
     
     
         24 . The method of    claim 20   , wherein said silicon/germanium layer comprises approximately 0.5 to 6% of germanium.  
     
     
         25 . The method of    claim 20   , wherein said silicon/germanium layer comprises approximately 5% of germanium.  
     
     
         26 . The method of    claim 20   , wherein said first silicon layer is an epitaxial silicon layer.  
     
     
         27 . The method of    claim 26   , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.  
     
     
         28 . The method of    claim 26   , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick.  
     
     
         29 . The method of    claim 20   , wherein said second silicon layer is an epitaxial silicon layer.  
     
     
         30 . The method of    claim 29   , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         31 . The method of    claim 29   , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick.  
     
     
         32 . The method of    claim 20    further including the step of etching back said second silicon substrate after said step of bonding said second silicon layer to said oxide layer.  
     
     
         33 . The method of    claim 20   , wherein said step of forming said oxide layer over said first semiconductor substrate further comprises thermally oxidizing said first semiconductor substrate.  
     
     
         34 . A memory cell, comprising: 
 a SOI substrate comprising a silicon/germanium layer formed between a first silicon layer and a second silicon layer, and an oxide layer bonded to said second silicon layer, said oxide layer being formed on a semiconductor substrate; and    a transistor including a gate fabricated on said SOI substrate and including source and drain regions fabricated adjacent to said gate.    
     
     
         35 . The memory cell of    claim 34   , wherein said silicon/germanium layer is an epitaxial silicon/germanium layer.  
     
     
         36 . The memory cell of    claim 34   , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.  
     
     
         37 . The memory cell of    claim 34   , wherein said silicon/germanium layer is approximately 200 Angstroms thick.  
     
     
         38 . The memory cell of    claim 34   , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.  
     
     
         39 . The memory cell of    claim 34   , wherein said silicon/germanium layer comprises approximately 5% germanium.  
     
     
         40 . The memory cell of    claim 34   , wherein said first silicon layer is an epitaxial silicon layer.  
     
     
         41 . The memory cell of    claim 40   , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.  
     
     
         42 . The memory cell of    claim 40   , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick.  
     
     
         43 . The memory cell of    claim 34   , wherein said second silicon layer is an epitaxial silicon layer.  
     
     
         44 . The memory cell of    claim 43   , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         45 . The memory cell of    claim 43   , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick.  
     
     
         46 . The memory cell of    claim 34   , wherein said oxide layer is approximately 1micron thick.  
     
     
         47 . The memory cell of    claim 34   , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.  
     
     
         48 . A processor system comprising: 
 a processor; and    an integrated circuit coupled to said processor and comprising a SOI substrate, said SOI substrate comprising a silicon/germanium layer formed between a first epitaxial silicon layer and a second epitaxial silicon layer, and an oxide layer bonded to said second epitaxial silicon layer, said oxide layer being formed on a semiconductor substrate.    
     
     
         49 . The processor system of    claim 48   , wherein said silicon/germanium layer is an epitaxially grown layer.  
     
     
         50 . The processor system of    claim 48   , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.  
     
     
         51 . The processor system of    claim 48   , wherein said silicon/germanium layer is approximately 200 Angstroms thick.  
     
     
         52 . The processor system of    claim 48   , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.  
     
     
         53 . The processor system of    claim 48   , wherein said silicon/germanium layer comprises approximately 5% germanium.  
     
     
         54 . The processor system of    claim 48   , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.  
     
     
         55 . The processor system of    claim 48   , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         56 . The processor system of    claim 48   , wherein said oxide layer is approximately 1micron thick.  
     
     
         57 . The processor system of    claim 48   , wherein said semiconductor substrate is a silicon substrate.  
     
     
         58 . The processor system of    claim 48   , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.  
     
     
         59 . The processor system of    claim 48   , wherein said integrated circuit is a memory device.  
     
     
         60 . The processor system of    claim 59   , wherein said memory device is a random access memory device.  
     
     
         61 . A SOI substrate comprising: 
 a first silicon substrate, said first silicon substrate having at least one layer of misfit dislocation regions formed therein at an intermediate location relative to first and second silicon surfaces of said substrate; and    an oxide layer formed over a second silicon substrate, said oxide layer being bonded to one of said first and second silicon surfaces of said first silicon substrate.    
     
     
         62 . The SOI substrate of    claim 61   , wherein said misfit dislocation regions are formed at an interface of two material layers which have different crystalline properties.  
     
     
         63 . The SOI substrate of    claim 62   , wherein said two material layers are a first silicon layer and a silicon/germanium layer.  
     
     
         64 . The SOI substrate of    claim 63   , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.  
     
     
         65 . The SOI substrate of    claim 63   , wherein said silicon/germanium layer is approximately 200 Angstroms thick.  
     
     
         66 . The SOI substrate of    claim 63   , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.  
     
     
         67 . The SOI substrate of    claim 63   , wherein said silicon/germanium layer comprises approximately 5% germanium.  
     
     
         68 . The SOI substrate of    claim 63   , wherein said first silicon layer is a first epitaxial silicon layer.  
     
     
         69 . The SOI substrate of    claim 68   , wherein said first epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         70 . The SOI substrate of    claim 68   , wherein said first epitaxial silicon layer is approximately 500 Angstroms thick.  
     
     
         71 . The SOI substrate of    claim 63    further comprising a second misfit dislocation region between said silicon/germanium layer and a second silicon layer, said silicon/germanium layer being in contact with said first silicon layer and said second silicon layer.  
     
     
         72 . The SOI substrate of    claim 71   , wherein said second silicon layer is a second epitaxial silicon layer.  
     
     
         73 . The SOI substrate of    claim 72   , wherein said second epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.  
     
     
         74 . The SOI substrate of    claim 72   , wherein said second epitaxial silicon layer is approximately 1,500 Angstroms thick.  
     
     
         75 . The SOI substrate of    claim 61   , wherein said oxide layer is approximately 1micron thick.  
     
     
         76 . The SOI substrate of    claim 61   , wherein said semiconductor substrate is a silicon substrate.  
     
     
         77 . The SOI substrate of    claim 61   , wherein said semiconductor substrate is a silicon-on-saphire substrate.  
     
     
         78 . The SOI substrate of    claim 61   , wherein said semiconductor substrate is a germanium substrate.  
     
     
         79 . The SOI substrate of    claim 61   , wherein said semiconductor substrate is a gallium-arsenide substrate.  
     
     
         80 . The SOI substrate of    claim 61   , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.  
     
     
         81 . A SOI structure comprising: 
 a first silicon/germanium layer formed between a first silicon layer and a second silicon layer, said first silicon/germanium layer being in contact with said first and second silicon layers;    a second silicon/germanium layer formed between a third silicon layer and said second silicon layer, said second silicon/germanium layer being in contact with said second and third silicon layers; and    an oxide layer formed over a semiconductor substrate, said oxide layer being in contact with said third silicon layer.    
     
     
         82 . The SOI structure of    claim 81   , wherein said first and second silicon/germanium layers are epitaxially grown layers.  
     
     
         83 . The SOI structure of    claim 81   , wherein said first and second silicon/germanium layers are approximately 100 to 300 Angstroms thick.  
     
     
         84 . The SOI structure of    claim 81   , wherein said first and second silicon/germanium layers are approximately 200 Angstroms thick.  
     
     
         85 . The SOI structure of    claim 81   , wherein said first and second silicon/germanium layers comprise approximately 0.5 to 6% germanium.  
     
     
         86 . The SOI structure of    claim 81   , wherein said first and second silicon/germanium layers comprise approximately 5% germanium.  
     
     
         87 . The SOI structure of    claim 81   , wherein said first silicon layer is an epitaxial silicon layer.  
     
     
         88 . The SOI structure of    claim 81   , wherein said first silicon layer is approximately 500 to 3,000 Angstroms thick.  
     
     
         89 . The SOI structure of    claim 81   , wherein said second silicon layer is an epitaxial silicon layer.  
     
     
         90 . The SOI structure of    claim 81   , wherein said second silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         91 . The SOI structure of    claim 81   , wherein said third silicon layer is an epitaxial silicon layer.  
     
     
         92 . The SOI structure of    claim 81   , wherein said third silicon layer is approximately 300 to 1,500 Angstroms thick.  
     
     
         93 . The SOI structure of    claim 81   , wherein said oxide layer is approximately 1micron thick.