Method for polysilicon crystalline line width measurement post etch in undoped-poly process

Abstract

A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of said polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon line; connecting a third probe to the substrate; connecting a first terminal of a capacitance meter to the first and second probes; connecting a second terminal of the capacitance meter to the third probe; and applying a direct current bias across the first and second probes. A capacitor may be connected between the first and second probes. Further steps include, connecting a fourth probe to a conductor that supports the substrate; and connecting the fourth probe to the third probe.

Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:  
     
         1 . A method of measuring a width of an undoped or lightly doped polysilicon line comprising the steps of: 
 generating carriers in the polysilicon line with an energy source;    measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and    determining a line width of said polysilicon line from the measured capacitance.    
     
     
         2 . The method of    claim 1   , wherein the line width determining step includes the steps of: 
 measuring a capacitance per unit area of said polysilicon line; and    determining a capacitance per unit length of said polysilicon line.    
     
     
         3 . The method of    claim 2   , wherein the capacitance per unit length determining step includes simulating a computer model of said polysilicon line.  
     
     
         4 . The method of    claim 1   , wherein the capacitance measuring steps includes the steps of: 
 electrically connecting first and second probes to said polysilicon line;    electrically connecting a third probe to a substrate on which said dielectric layer is formed;    electrically connecting a first terminal of a capacitance meter to said first probe;    electrically connecting a second terminal of said capacitance meter to said third probe; and    applying a direct current bias across said first and second probes.    
     
     
         5 . The method of    claim 4    further comprising connecting a capacitor between said first and second probes.  
     
     
         6 . The method of    claim 4    further comprising the steps of: 
 electrically connecting a fourth probe to a conductor that supports said substrate; and  
 electrically connecting said fourth probe to said third probe.  
 
     
     
         7 . A method of lowering contact resistance of polysilicon comprising the steps of: 
 electrically connecting two probes to said polysilicon; and    applying a direct current bias across the two probes.    
     
     
         8 . The method of    claim 7    further comprising connecting a capacitor between said two probes.  
     
     
         9 . The method of    claim 7   , wherein the applying step lowers a small-signal impedance of said polysilicon.  
     
     
         10 . The method of    claim 7    further comprising generating carriers in the polysilicon with an energy source.  
     
     
         11 . A method of measuring capacitance between a substrate having a dielectric layer formed thereon and a polysilicon formed on the dielectric layer comprising the steps of: 
 electrically connecting first and second probes to said polysilicon;    electrically connecting a third probe to said substrate;    electrically connecting a first terminal of a capacitance meter to said first probe;    electrically connecting a second terminal of said capacitance meter to said third probe; and    applying a direct current bias across said first and second probes.    
     
     
         12 . The method of    claim 11    further comprising connecting a capacitor between said first and second probes.  
     
     
         13 . The method of    claim 11    further comprising generating carriers in the polysilicon with an energy source.  
     
     
         14 . The method of    claim 11    further comprising the steps of: 
 electrically connecting a fourth probe to a conductor that supports said substrate; and  
 electrically connecting said fourth probe to said third probe.  
 
     
     
         15 . A method of providing a contact to a substrate wherein said contact provides both zero frequency and higher frequency electrical connection to said substrate, said method comprising connecting said contact to said substrate and to a conductor that is separated from said substrate by a dielectric layer.