Semiconductor non-volatile memory device and corresponding fabrication process

Abstract

A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

That which is claimed is:  
     
         1 . Semiconductor non-volatile memory device comprising a silicon-based semiconductor substrate (SB) containing a source region (S) and a drain region (D), a control gate (CG) and a floating gate (FG), characterized in that the floating gate (FG) extends between the source (S) and drain (D) regions formed in the substrate (SB) and the control gate (CG) lies above the floating gate (FG) so as to be proud of the source and drain regions.  
     
     
         2 . Device according to    claim 1   , characterized in that the substrate (SB) has a lower part lying beneath the source and drain regions and a channel region (CR) lying above the lower part of the substrate between the source and drain regions and in that the floating gate (FG) is formed from a semiconductor region (SCS) overdoped with respect to the channel region, lying above the channel region (CR) and isolated from this channel region and from the source and drain regions by an insulating layer (OX 1 ).  
     
     
         3 . Device according to    claim 2   , characterized in that it includes an additional insulating layer (OX 3 ) placed between the channel region (CR) and the lower part of the substrate (SB).  
     
     
         4 . Process for fabricating a semiconductor non-volatile memory device, characterized in that it comprises the formation, on an initial silicon substrate (ISB) surrounded by an isolating peripheral region (BX), of a first layer ( 1 ) of a material that can be removed selectively with respect to the silicon; the formation on the said first layer ( 1 ) of a silicon second layer ( 2 ) overdoped with respect to the initial substrate; the formation of a gate oxide layer ( 3 ) on the second layer ( 2 ); the formation, on the gate oxide layer ( 3 ), of a control gate (CG) bearing at its two opposed ends on the isolating peripheral region (BX); the etching, along two opposed sidewalls of the control gate, of the gate oxide layer ( 3 ), of the second layer ( 2 ), of the first layer ( 1 ) and of an upper part of the initial substrate (ISB) so as to form cavities (CAV); selective etching of the first layer ( 1 ) so as to form a tunnel (TNL) between the second layer ( 2 ) and the initial substrate (ISB); a step of insulating the second layer ( 2 ), comprising the formation of an insulating layer on the walls of the second layer ( 2 ) and in at least part of the tunnel (TNL); the filling of the cavities with silicon (ESR); and the formation of the source and drain regions in the filled cavities, on each side of the second etched layer (SCS) forming a floating gate (FG).  
     
     
         5 . Process according to    claim 4   , characterized in that the insulating step comprises coating the walls of the tunnel with the insulating layer ( 301 ,  302 ;  402 ,  404 ), the inside of the tunnel being empty.  
     
     
         6 . Process according to    claim 4   , characterized in that the insulating step comprises completely filling the tunnel with the insulating layer ( 202 ).  
     
     
         7 . Process according to one of    claims 4    to    6   , characterized in that the insulating step also includes the formation of the insulating layer in the bottom of the cavities (CAV) and in that part of the insulating layer formed in the bottom of the cavities is removed before the cavities are filled with silicon.  
     
     
         8 . Process according to    claim 7   , characterized in that part of the insulating layer formed in the bottom of the cavities (CAV) is removed by anisotropic etching.  
     
     
         9 . Process according to    claim 7   , characterized in that part of the insulating layer formed in the bottom of the cavities (CAV) is removed by chemical etching in a wet bath.  
     
     
         10 . Process according to    claim 9    taken in combination with    claim 5   , characterized in that, before oxidizing the tunnel, selected ions are implanted into the bottom of the cavities so as to retard the oxidation of the silicon and to obtain, after the insulating step, a thinner insulating layer ( 401 ) in the bottom of the cavities than inside the tunnel.  
     
     
         11 . Process according to one of    claims 4    to    10   , characterized in that the silicon is grown by selective epitaxy during the cavity-filling step, the silicon (ESR) also filling, optionally, the inside of the tunnel.