System including phase lock loop circuit

Abstract

A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects that the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcedly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.

What is claimed is:  
     
         1 . A system comprising: 
 a first switch which controls feed of a first power supply voltage;    a second switch which controls feed of a second power supply voltage;    a PLL circuit which includes a first circuit that is operated by said first power supply voltage, and a second circuit that is operated by said second power supply voltage; and    a setting circuit which detects the operating state of said PLL circuit, and which brings said PLL circuit into a predetermined state in accordance with a result of the detection.    
     
     
         2 . A system according to    claim 1   , wherein said PLL circuit and said setting circuit are provided in a single semiconductor integrated circuit device.  
     
     
         3 . A system according to    claim 2   , wherein: 
 said first circuit includes a phase comparator circuit which detects a phase difference between a reference clock signal and a feedback clock signal, a control circuit which produces a control voltage conforming to an output of said phase comparator circuit, and a voltage-controlled oscillator circuit which generates a clock signal at a frequency conforming to said control voltage; and    the second circuit includes a circuit which feeds an output of the voltage-controlled oscillator circuit as said feedback clock signal.    
     
     
         4 . A system according to    claim 3   , wherein said setting circuit includes: 
 a comparison circuit which detects a value of said control voltage; and    means for lowering said control voltage in accordance with an output of said comparison circuit.    
     
     
         5 . A system according to    claim 3   , further comprising: 
 a second semiconductor integrated circuit device which is operated in accordance with a clock signal;    said second circuit including a circuit which feeds said output of said voltage-controlled oscillator circuit as the clock signal of said second semiconductor integrated circuit.    
     
     
         6 . A system comprising: 
 a wiring line which transfers a feedback clock signal; and    a semiconductor integrated circuit device which includes a first external terminal that receives a reference clock signal, a second external terminal that receives the feedback clock signal, a third external terminal that outputs said feedback clock signal, and a circuit that is connected to the first external terminal, the second external terminal and the third external terminal and that is operated as a PLL circuit by connecting said second external terminal and said third external terminal through said wiring line;    said semiconductor integrated circuit device including a detection and setting circuit which detects an operating state of the PLL circuit, and which brings said PLL circuit into a predetermined state in accordance with the operating state.    
     
     
         7 . A system according to    claim 6   , wherein said circuit includes a phase comparator circuit which detects a phase difference between the reference clock signal and said feedback clock signal, a control circuit which produces a control voltage conforming to an output of said phase comparator circuit, a voltage-controlled oscillator circuit which generates a clock signal of a frequency conforming to the control voltage; and a circuit which generates said feedback clock signal fed to said third external terminal in accordance with the clock signal outputted from the voltage-controlled oscillator circuit.  
     
     
         8 . A system according to    claim 7   , wherein the detection and setting circuit includes: 
 a comparison circuit which detects a value of said control voltage; and    means for lowering said control voltage in accordance with the output of said comparison circuit.    
     
     
         9 . A system according to    claim 8   , wherein: 
 said semiconductor integrated circuit device includes a fourth external terminal from which a clock signal conforming to said clock signal outputted from said voltage-controlled oscillator circuit is outputted;    said system further comprises a second semiconductor integrated circuit device which is operated in accordance with the clock signal outputted from the fourth terminal.    
     
     
         10 . A system according to    claim 1   , wherein: 
 said first circuit includes a phase comparator circuit which detects a phase difference between a reference clock signal and a feedback clock signal, a control circuit which produces a control voltage conforming to an output of said phase comparator circuit, and a voltage-controlled oscillator circuit which generates a clock signal of a frequency conforming to the control voltage; and    said second circuit includes a circuit which feeds an output of said voltage-controlled oscillator circuit as the feedback clock signal.    
     
     
         11 . A system according to    claim 10   , wherein: 
 said first circuit and said second circuit are provided in a single semiconductor integrated circuit device; and    a wiring line which feeds said first circuit with said feedback clock signal outputted from said second circuit is laid outside said semiconductor integrated circuit device.