Eeprom with erasing gate adjacent floating gate and control gate

Abstract

A structure of a floating gate type EEPROM capable of implementing micromachining less than submicron and a method for fabricating it are disclosed. Since a silicon oxide film 3 for element isolation is embedded in an P-type Si substrate 1 , as compared with the case where the element isolation region is formed on the P-type Si substrate 1 , a level difference between the P-type Si substrate 1 and a floating gate electrode 6 , control gate electrode 8 and erasing gate electrode 12 can be reduced remarkably. This solves a problem of etching remainder during the dry etching of each electrode. In addition, the depth of focus in lithography can be easily assured. This realizes a floating gate type EEPROM equipped with an erasing gate which is so fine as to be less than submicron.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an element isolation region embedded in a semiconductor substrate having a first conductivity type;    a source region and a drain region formed in an element forming region surrounded by said element isolation region, said source region and drain region having a second conductivity type opposite to said first conductivity type;    a first insulating film formed on said element forming region;    a floating gate electrode formed on said first insulating film;    a second insulating film formed on said floating gate electrode;    a control gate electrode formed on said second insulating film;    a third insulating film formed on said floating gate electrode; and    an erasing gate electrode formed so as face said floating gate electrode through said third insulating film to be a tunneling medium.    
     
     
         2 . The semiconductor memory device according to    claim 1   , wherein said third insulating film is formed on a side surface and a part of an upper surface of said floating gate electrode.  
     
     
         3 . The semiconductor memory device according to    claim 1   , further comprising a peripheral circuit formed on a surface of said semiconductor substrate, wherein a wiring layer of said peripheral circuit and said erasing gate electrode are made of a conductive layer formed by a same step.  
     
     
         4 . A semiconductor memory device comprising: 
 an insulating film for element isolation formed at a prescribed portion on a semiconductor substrate having a first conductivity type;    a semiconductor layer embedded in a portion surrounded by said insulating film on said semiconductor substrate;    a source region and a drain region formed in said semiconductor layer and having a second conductivity type opposite to said first conductivity type;    a first insulating film formed at a prescribed area of said semiconductor layer;    a floating gate electrode formed on said first insulating film;    a second insulating film formed on said floating gate electrode;    a control gate electrode formed on said second insulating film;    a third insulating film formed on said floating gate electrode; and    an erasing gate electrode formed on said third insulating film so as to face said floating gate electrode.    
     
     
         5 . The semiconductor memory device according to    claim 4   , wherein said second insulating film is formed on a side and a portion of an upper surface of said floating gate electrode.  
     
     
         6 . The semiconductor memory device according to    claim 4   , further comprising a peripheral circuit formed on a surface of said semiconductor substrate, wherein a wiring layer of said peripheral circuit and said erasing gate electrode are formed of the same conductive layer.