Delay circuit applied to semiconductor memory device having auto power-down function

Abstract

A delay circuit comprises a charge/discharge circuit and a logic circuit. The charge/discharge circuit is used to moderate a slope of change of an input signal. The logic circuit receives a charge/discharge signal output from the charge/discharge circuit, and is used to change an output signal of the logic circuit when the charge/discharge signal exceeds a threshold value of the logic circuit. A time constant in the charge/discharge circuit is varied in accordance with the change in the output signal of the logic circuit. This serves to alleviate the malfunctioning and timing constraint problems that occur after the threshold value of the next-stage circuit (logic circuit) is exceeded.

What is claimed is:  
     
         1 . A delay circuit comprising: 
 a charge/discharge circuit for moderating a slope of change of an input signal; and    a logic circuit, receiving a charge/discharge signal output from said charge/discharge circuit, for changing an output signal of said logic circuit when the charge/discharge signal exceeds a threshold value of said logic circuit, wherein:    a time constant in said charge/discharge circuit is varied in accordance with the change in the output signal of said logic circuit.    
     
     
         2 . A delay circuit as claimed in    claim 1   , wherein said charge/discharge circuit comprises a switch element whose one end is connected to an input of said logic circuit, and a capacitor element whose one end is connected to the other end of said switch element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary the time constant of said charge/discharge circuit due to said capacitor element.  
     
     
         3 . A delay circuit as claimed in    claim 2   , wherein said switch element is controlled in such a manner as to be switched OFF by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.  
     
     
         4 . A delay circuit as claimed in    claim 2   , wherein there are provided a plurality of said capacitor elements whose connection to the input of said logic circuit is controlled by said switch element, and said plurality of capacitor elements are arranged in parallel with each other.  
     
     
         5 . A delay circuit as claimed in    claim 4   , wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to a prescribed power supply line.  
     
     
         6 . A delay circuit as claimed in    claim 4   , wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to an output of a driver circuit supplied with a prescribed control signal.  
     
     
         7 . A delay circuit as claimed in    claim 1   , wherein said charge/discharge circuit is inserted in an input of said logic circuit, and comprises a resistor element for supplying said input signal via said resistor element, and a switch element disposed in parallel with said resistor element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary the time constant of said charge/discharge circuit due to said resistor element.  
     
     
         8 . A delay circuit as claimed in    claim 7   , wherein said switch element is controlled in such a manner as to be switched ON by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.  
     
     
         9 . A delay circuit as claimed in    claim 7   , wherein there are provided a plurality of said switch elements and a plurality of said resistor elements whose short-circuiting with the input of said logic circuit is controlled by said switch element, and said plurality of switch elements and said plurality of resistor elements are respectively arranged in series with each other.  
     
     
         10 . A delay circuit as claimed in    claim 9   , wherein said plurality of switch elements for controlling the short-circuiting of said plurality of resistor elements are each controlled for switching, by the output signal of said logic circuit.  
     
     
         11 . A delay circuit as claimed in    claim 1   , wherein said charge/discharge circuit includes a current source, and a current flowing through said current source is controlled by the output signal of said logic circuit.  
     
     
         12 . A delay circuit as claimed in    claim 11   , wherein the current flowing through said current source is controlled so that the current increases when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.  
     
     
         13 . A delay circuit as claimed in    claim 1   , wherein said logic circuit comprises a comparator, a first input terminal of which is supplied with the charge/discharge signal from said charge/discharge circuit, and a second input terminal of which is supplied with a reference voltage, wherein a control is carried out to vary the reference voltage in accordance with the output signal of said logic circuit.  
     
     
         14 . A delay circuit as claimed in    claim 1   , wherein said logic circuit comprises a CMOS inverter.  
     
     
         15 . A delay circuit as claimed in    claim 1   , wherein said capacitor element is constituted as a CMOS capacitor.  
     
     
         16 . A semiconductor memory device having: 
 a cell matrix having a plurality of memory cells;    a data latch for latching readout data output from said cell matrix;    an address transfer detection circuit for detecting an address signal change;    a delay circuit, outputting a latch control signal to said data latch in accordance with an output signal of said address transfer detection circuit, for controlling said data latch to output the readout data in synchronism with the latch control signal, wherein said delay circuit comprises:    a charge/discharge circuit for moderating a slope of change of an input signal; and    a logic circuit, receiving a charge/discharge signal output from said charge/discharge circuit, for changing an output signal of said logic circuit when the charge/discharge signal exceeds a threshold value of said logic circuit, wherein:    a time constant in said charge/discharge circuit is varied in accordance with the change in the output signal of said logic circuit.    
     
     
         17 . A semiconductor memory device as claimed in    claim 16   , wherein said charge/discharge circuit comprises a switch element whose one end is connected to an input of said logic circuit, and a capacitor element whose one end is connected to the other end of said switch element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary the time constant of said charge/discharge circuit due to said capacitor element.  
     
     
         18 . A semiconductor memory device as claimed in    claim 17   , wherein said switch element is controlled in such a manner as to be switched OFF by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.  
     
     
         19 . A semiconductor memory device as claimed in    claim 17   , wherein there are provided a plurality of said capacitor elements whose connection to the input of said logic circuit is controlled by said switch element, and said plurality of capacitor elements are arranged in parallel with each other.  
     
     
         20 . A semiconductor memory device as claimed in    claim 19   , wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to a prescribed power supply line.  
     
     
         21 . A semiconductor memory device as claimed in    claim 19   , wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to an output of a driver circuit supplied with a prescribed control signal.  
     
     
         22 . A semiconductor memory device as claimed in    claim 16   , wherein said charge/discharge circuit is inserted in an input of said logic circuit, and comprises a resistor element for supplying said input signal via said resistor element, and a switch element disposed in parallel with said resistor element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary the time constant of said charge/discharge circuit due to said resistor element.  
     
     
         23 . A semiconductor memory device as claimed in    claim 22   , wherein said switch element is controlled in such a manner as to be switched ON by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.  
     
     
         24 . A semiconductor memory device as claimed in    claim 22   , wherein there are provided a plurality of said switch elements and a plurality of said resistor elements whose short-circuiting with the input of said logic circuit is controlled by said switch element, and said plurality of switch elements and said plurality of resistor elements are respectively arranged in series with each other.  
     
     
         25 . A semiconductor memory device as claimed in    claim 24   , wherein said plurality of switch elements for controlling the short-circuiting of said plurality of resistor elements are each controlled for switching, by the output signal of said logic circuit.  
     
     
         26 . A semiconductor memory device as claimed in    claim 16   , wherein said charge/discharge circuit includes a current source, and a current flowing through said current source is controlled by the output signal of said logic circuit.  
     
     
         27 . A semiconductor memory device as claimed in    claim 16   , wherein the current flowing through said current source is controlled so that the current increases when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.  
     
     
         28 . A semiconductor memory device as claimed in    claim 16   , wherein said logic circuit comprises a comparator, a first input terminal of which is supplied with the charge/discharge signal from said charge/discharge circuit, and a second input terminal of which is supplied with a reference voltage, wherein a control is carried out to vary the reference voltage in accordance with the output signal of said logic circuit.  
     
     
         29 . A semiconductor memory device as claimed in    claim 16   , wherein said logic circuit comprises a CMOS inverter.  
     
     
         30 . A semiconductor memory device as claimed in    claim 16   , wherein said capacitor element is constituted as a CMOS capacitor.  
     
     
         31 . A semiconductor memory device as claimed in    claim 16   , wherein said semiconductor memory device is a flash EEPROM.