Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

Abstract

A logic circuit performs a predetermined logic operation by supplying charge to an external load or putting out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area. Adjacent ones of the logic circuits have a common source diffusion layer so that the load capacitance with respect to the inverse signal can be significantly reduced, thus enabling the high speed operation.

What is claimed is:  
     
         1 . A logic circuit performing a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals, said logic circuit comprising: 
 at least a first transistor for supplying charge through an output terminal to said external load; and    at least a second transistor for pulling out the charge from said load through said output terminal,    one of said first and second transistors being constituted by a MOS field-effect transistor having a drain connected to said output terminal,    said MOS field-effect transistor having a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of said MOS field-effect transistor.    
     
     
         2 . The logic circuit according to    claim 1   , wherein said first and second transistors are complementary MOS field-effect transistors.  
     
     
         3 . The logic circuit according to    claim 1   , wherein said first or second transistor that is other than said MOS field-effect transistor is a bipolar transistor.  
     
     
         4 . The logic circuit according to    claim 2   , which further comprises a bipolar/CMOS transistor structure which outputs an output signal of said logic circuit through an output stage constituted by a series circuit of a bipolar transistor and a MOS field-effect transistor.  
     
     
         5 . The logic circuit according to    claim 3   , which further comprises a bipolar/CMOS transistor structure which outputs an output signal of said logic circuit through an output stage constituted by a series circuit of a bipolar transistor and a MOS field-effect transistor.  
     
     
         6 . The logic circuit according to    claim 1   , which further comprises an inverse signal generating circuit for generating an inverse signal inputted to the source of said MOS field-effect transistor, 
 said inverse signal generating circuit for generating said inverse signal, in which the logic amplitude thereof is reduced according to a down-threshold in two series n-channel MOS field-effect transistors connected between a power supply line and a reference potential point, by inputting complimentary signals in phase and in inverse phase with respect to said inverse signal to the gates of said n-channel MOS field-effect transistors, respectively.    
     
     
         7 . The logic circuit according to    claim 1   , which further comprises: 
 a third transistor in parallel with said first transistor, said first transistor supplying charge to said load, a signal in phase with respect to a logic output signal being fed-back to a control electrode of said third transistor.    
     
     
         8 . A logic circuit comprising: 
 an output stage control transistor means having a drain; and    a first n-channel MOS field-effect transistor having a drain connected to said drain of said output stage control transistor means,    said first input signal and the inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said first n-channel MOS field-effect transistor,    the drains of said output stage control transistor means and said first n-channel MOS field-effect transistor being connected as said common node connected to an output stage.    
     
     
         9 . The logic circuit according to    claim 8   , in which said output stage control transistor means comprises two parallel p-channel MOS field-effect transistors receiving a first input signal and a second input signal, respectively.  
     
     
         10 . The logic circuit according to    claim 8   , in which said output stage comprises: 
 a bipolar transistor having a collector connected to a high potential point, and    a second n-channel MOS field-effect transistor having a drain connected to an emitter of said bipolar transistor,    the drain of said first n-channel MOS field-effect transistor being connected to a base of said bipolar transistor, said node of the emitter of said bipolar transistor and the drain of said second n-channel MOS field-effect transistor being connected to an output terminal,    said first input signal and the inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said second n-channel MOS field-effect transistor.    
     
     
         11 . The logic circuit according to    claim 9   , in which said output stage control transistor means comprises a p-channel MOS field-effect transistor always being held “on” with the gate thereof held at a constant potential.  
     
     
         12 . The logic circuit according to    claim 10   , in which said output stage control transistor means comprises a p-channel MOS field-effect transistor always being held “on” with the gate thereof held at a constant potential.  
     
     
         13 . A logic circuit comprising: 
 two bipolar transistors having bases respectively receiving an inverse signal inverse to a first input signal and an inverse signal inverse to a second input signal; and    an n-channel MOS field-effect transistor having a drain connected to a common node of emitters of said two bipolar transistors,    said first input signal and said inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said n-channel MOS field-effect transistor,    said emitters of said two bipolar transistors and the drain of said n-channel MOS field-effect transistor being connected as a common node to an output terminal.    
     
     
         14 . A logic circuit comprising: 
 two parallel n-channel MOS field-effect transistors having gates respectively receiving a first input signal and a second input signal; and    a first n-channel MOS field-effect transistor having a drain connected to a common node of the drains of said n-channel MOS field-effect transistors,    said first input signal and the inverse signal inverse to said second input signal being inputted to a gate and a source, respectively, of said first p-channel MOS field-effect transistor,    the drains of said n-channel MOS field-effect transistors and said first p-channel MOS field-effect transistor being connected as a common node connected to an output stage.    
     
     
         15 . The logic circuit according to    claim 14   , in which said output stage comprises: 
 a bipolar transistor having a collector connected to a high potential point;    a third n-channel MOS field-effect transistor having a drain thereof connected to an emitter of said bipolar transistor and a source connected to a reference potential point; and    a fourth n-channel MOS field-effect transistor connected in parallel with said third n-channel MOS field-effect transistor,    said drain of said first p-channel MOS field-effect transistor being connected to the base of said bipolar transistor, said node of the emitter of said bipolar transistor and the drains of said third and fourth n-channel MOS field-effect transistors being connected to an output terminal,    said first and second input signals being inputted to the gates of said third and fourth n-channel MOS field-effect transistors, respectively.    
     
     
         16 . A logic circuit comprising: 
 an n-channel MOS field-effect transistor having a gate receiving a first input signal and a source and a drain respectively receiving an inverse signal inverse to a second input signal being inputted to the source and the drain, respectively; and    an output stage control transistor means having a drain connected to the drain of said n-channel MOS field-effect transistor,    said common node of drains of said n-channel MOS field-effect transistor and said output stage control transistor means being coupled to an inverter having a CMOS transistor structure for outputting an output signal.    
     
     
         17 . The logic circuit according to    claim 16   , in which said output stage control transistor means comprises two parallel p-channel MOS field-effect transistors having gates receiving said first and second input signals, respectively.  
     
     
         18 . The logic circuit according to    claim 16   , in which said output stage control transistor means comprises a first p-channel MOS field-effect transistor being always held “on” with the gate thereof held at a constant potential.  
     
     
         19 . The logic circuit according to    claim 18   , which further comprises: 
 a second p-channel MOS field-effect transistor connected in parallel with said first p-channel MOS field-effect transistor, and structured such that a signal in phase with the signal from the drain of said n-channel MOS field-effect transistor is fed-back to the gate of said second p-channel MOS field-effect transistor.    
     
     
         20 . The logic circuit according to    claim 17   , which further comprises an inverse signal generating circuit for generating an inverse signal inputted to the source of said n-channel MOS field-effect transistor, 
 said inverse signal generating circuit for generating said inverse signal, in which the logic amplitude thereof is reduced according to a down-threshold in two series n-channel MOS field-effect transistors connected between a power supply line and a reference potential point, by inputting complimentary signals in phase and in inverse phase with respect to said inverse signal to the gates of said n-channel MOS field-effect transistors, respectively.    
     
     
         21 . The logic circuit according to    claim 18   , which further comprises an inverse signal generating circuit for generating an inverse signal inputted to the source of said n-channel MOS field-effect transistor, 
 said inverse signal generating circuit for generating said inverse signal, in which the logic amplitude thereof is reduced according to a down-threshold in two series n-channel MOS field-effect transistors connected between a power supply line and a reference potential point, by inputting complimentary signals in phase and in inverse phase with respect to said inverse signal to the gates of said n-channel MOS field-effect transistors, respectively.    
     
     
         22 . The logic circuit according to    claim 19   , which further comprises an inverse signal generating circuit for generating an inverse signal inputted to the source of said n-channel MOS field-effect transistor, 
 said inverse signal generating circuit for generating said inverse signal, in which the logic amplitude thereof is reduced according to a down-threshold in two series n-channel MOS field-effect transistors connected between a power supply line and a reference potential point, by inputting complimentary signals in phase and in inverse phase with respect to said inverse signal to the gates of said n-channel MOS field-effect transistors, respectively.    
     
     
         23 . A semiconductor integrated circuit comprising a decoder circuit provided on a chip, said decoder circuit having an array of a plurality of logic circuits performing a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals, each of said logic circuits comprising: 
 at least a first transistor for supplying charge through an output terminal to said external load; and    at least a second transistor for pulling out the charge from said load through said output terminal,    one of said first and second transistors being constituted by a MOS field-effect transistor having a drain connected to said output terminal,    said MOS field-effect transistor having a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal to a gate of said MOS field-effect transistor,    said MOS field-effect transistor being arranged such that the adjacent ones of said logic circuits share a source diffusion layer.