Multi-chip memory apparatus and associated method

Abstract

A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

What is claimed is:  
     
         1 . A multi-chip integrated circuit package comprising: 
 a memory integrated circuit, said memory integrated circuit having a selected number of storage locations for storing data therein, said memory chip including memory chip bond pads;    a non-memory integrated circuit, said integrated circuit having non-memory chip bond pads a subset thereof positioned to abut together with the memory chip bond pads; and    an interconnector formed between each corresponding memory integrated circuit bond pad and non-memory integrated circuit bond pad, said interconnector providing electrical connection between said memory chip bond pad and said non-memory chip bond pad.    
     
     
         2 . The multi-chip integrated circuit package of    claim 1    wherein the interface formed by said interconnector appears to said memory chip to be of electrical characteristics substantially corresponding to an internal node of said memory chip.  
     
     
         3 . The multi-chip integrated circuit package of    claim 1    wherein the interface formed by said interconnector appears to said logic chip to be of electrical characteristics substantially corresponding to an internal node of said logic chip.  
     
     
         4 . The multi-chip integrated circuit package of    claim 1    wherein the interconnector between the memory and non-memory integrated circuits is comprised of solder balls.  
     
     
         5 . The multi-chip integrated circuit package of    claim 1    wherein the interconnector between the memory and non-memory integrated circuits is comprised of gold balls.  
     
     
         6 . The multi-chip integrated circuit package of    claim 1    wherein said non-memory integrated circuit further comprises circuit-connection nodes, wherein said multi-chip integrated circuit package further comprises: 
 an enclosure for enclosing both said memory integrated circuit and said non-memory integrated circuit, external nodes positioned external to said enclosure, and an electrical connection connecting said circuit-connection nodes and external nodes together.  
 
     
     
         7 . The multi-chip integrated circuit package of    claim 6    wherein the said enclosure is plastic.  
     
     
         8 . The multi-chip integrated circuit package of    claim 6    wherein the said enclosure is ceramic.  
     
     
         9 . The multi-chip integrated circuit package of    claim 1    wherein the memory chip is optimized to provide optimum drive to the low capacitance interface.  
     
     
         10 . The multi-chip integrated circuit package of    claim 1    wherein the non-memory chip is optimized to provide optimum drive to the low capacitance interface.  
     
     
         11 . The multi-chip integrated circuit package of    claim 1    wherein said memory integrated circuit comprises a DRAM (dynamic read/write memory).  
     
     
         12 . The multi-chip integrated circuit package of    claim 1    wherein said interconnector comprises solder balls electrically connected, and mechanically affixed, to said memory integrated circuit.  
     
     
         13 . The multi-chip integrated circuit package of    claim 1    wherein said interconnector comprises solder balls electrically connected, and mechanically affixed, to said non-memory integrated circuit.  
     
     
         14 . in a multi-chip integrated circuit having a memory chip, the memory chip including a memory-chip face surface, an improvement of a logic chip to which the memory chip is mountable, the logic chip having a logic-chip face surface, said logic chip comprising: 
 logic circuitry for performing a logical function, said logic circuitry including components extending to the logic-chip face surface;    a selected number of logic-chip interconnector elements formed upon the logic-chip face surface; and    a selected number of memory-chip interconnector elements formed upon the memory-chip face surface, said memory chip interconnectors corresponding in number with the memory-chip interconnector elements and positioned such that, when the memory chip is positioned to be mounted upon the logic chip, said logic-chip interconnector elements and said memory-chip interconnector elements are aligned with one another, together to form an electrical interface between the memory chip and said logic circuitry which bonds said memory chip directly onto said logic circuitry, the electrical interface formed thereby of electrical characteristics appearing, to said logic circuitry, to substantially correspond to an internal node of said logic circuitry.    
     
     
         15 . An integrated circuit comprising: 
 a memory chip, said memory chip having a selected number of storage locations for storing data therein, said memory chip Including a memory-chip face surface;    a logic chip having a logic-chip face surface positioned to abut together with the memory-chip face surface; and    an interconnector forming interface positioned between said memory chip and said logic chip, said interconnector for electrically connecting said memory chip together with said logic chip which directly bonds said memory chip and said logic chip theretogether, the interface formed by said interconnector appearing to said memory chip to be of electrical characteristics substantially corresponding to an internal node of said memory chip.    
     
     
         16 . The integrated circuit of    claim 15    wherein said memory chip comprises a DRAM (dynamic random access memory).  
     
     
         17 . The integrated circuit of    claim 15    wherein said interconnector exhibits capacitance levels of less than ten picofarads.  
     
     
         18 . A method for fabricating an integrated circuit, said method comprising the steps of: 
 providing a memory chip having a selected number of storage locations for storing data therein, the memory chip including a memory-chip face surface;    providing a logic chip having logic circuitry for performing a logic function, the logic chip including a logic-chip face surface;    forming an interconnector upon at least one of the memory-chip face surface and the logic-chip face surface;    connecting the memory chip and the logic chip by positioning the memory chip and the logic chip in abutting engagement by way of the interconnector formed during said step of forming.    
     
     
         19 . The method of    claim 18    wherein the memory chip provided during said step of providing the memory chip comprises a DRAM (dynamic random access memory).  
     
     
         20 . The method of    claim 18    wherein said step of forming comprises positioning interconnector elements upon both the logic-chip face surface and the memory-chip face surface.  
     
     
         21 . The method of    claim 18    wherein said step of connecting further comprises, subsequent to positioning the memory chip and the logic chip in the abutting engagement, soldering the interconnector formed during said step of forming.