Method and apparatus for wiring integrated circuits with multiple power buses based on performance

Abstract

A method and structure for designing a circuit, including identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply, and redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply. The higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.

What is claimed is:  
     
         1 . A method for designing a circuit, comprising: 
 identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply; and    redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply,    wherein the higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.    
     
     
         2 . The method according to    claim 1   , wherein said performance criteria includes a timing margin criteria.  
     
     
         3 . The method according to    claim 1   , wherein said redesigning includes changing a granularity of logic paths of said paths in said circuit.  
     
     
         4 . The method according to    claim 2   , wherein said redesigning includes changing a granularity of logic paths of said paths in said circuit.  
     
     
         5 . An apparatus for designing a circuit, comprising: 
 means for identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply; and    means for redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply,    wherein the higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.    
     
     
         6 . The apparatus according to    claim 5   , wherein said performance criteria includes a timing margin criteria.  
     
     
         7 . The apparatus according to    claim 5   , wherein said means for redesigning includes means for changing a granularity of logic paths of said paths in said circuit.  
     
     
         8 . The apparatus according to    claim 2   , wherein said means for redesigning includes means for changing a granularity of logic paths of said paths in said circuit.  
     
     
         9 . An apparatus comprising: 
 a plurality of devices, at least one of the devices including: 
 a first input coupled to a first power supply for controlling an amount of current supplied to the apparatus from the first power supply; and  
 a second input for receiving a signal from at least one low power signal path, the low power signal path being coupled to a second power supply having a higher voltage than the first power supply,  
   wherein said at least one of the devices has an increased voltage threshold compared to others of the plurality of devices for minimizing an amount of current provided to the apparatus from the first power supply.    
     
     
         10 . The apparatus of    claim 9   , wherein said at least one of the devices controls said amount of current supplied to the apparatus in response to receiving at said first input said signal from said at least one low power signal path.  
     
     
         11 . A method of optimizing performance and minimizing power dissipation of a plurality of integrated circuits, comprising: 
 simulating the integrated circuits by wiring said integrated circuits with a first voltage power supply,    identifying paths between said integrated circuits not meeting a delay, margin criteria;    wiring integrated circuits having paths not meeting said delay margin criteria with a second voltage power supply;    determining and increasing a magnitude of load threshold voltages of all second voltage circuits having input signals emanating from first voltage bus circuits; and    re-simulating the integrated circuits and determining whether all logic paths meet said delay margin criteria and power criteria.    
     
     
         12 . The method according to    claim 11   , further comprising: 
 for said logic paths not meeting said power criteria, using finer granularity of logic paths to isolate slow circuit paths; and    repeating said simulating, identifying, wiring, determining, and re-simulating steps.    
     
     
         13 . The method according to    claim 12   , further comprising: 
 performing a logical-to-physical translation of the integrated circuit topology for creating a high load threshold adjust mask.    
     
     
         14 . The method according to    claim 11   , wherein said second voltage is higher than said first voltage.  
     
     
         15 . The method according to    claim 11   , wherein said load threshold voltage comprises a P-type field effect transistor (PFET) load threshold voltage.  
     
     
         16 . A system for optimizing performance and minimizing power dissipation of a plurality of integrated circuits, comprising: 
 means for simulating the integrated circuits by wiring said integrated circuits with a first voltage power supply;    means for identifying paths between said integrated circuits not meeting a delay margin criteria;    means for wiring integrated circuits having paths not meeting said delay margin criteria with a second voltage power supply;    means for determining and increasing a magnitude of load threshold voltages of all second voltage circuits having input signals emanating from first voltage bus circuits; and    means for re-simulating the integrated circuits and determining whether all logic paths meet said delay margin criteria and power criteria.    
     
     
         17 . The method according to    claim 16   , further comprising: 
 for said logic paths of meeting said power criteria, using finer granularity of logic paths to isolate slow circuit paths; and    repeating said simulating, identifying, wiring, determining, and re-simulating, steps.    
     
     
         18 . The method according to    claim 17   , further comprising: 
 performing a logical-to-physical translation of the integrated circuit topology for creating a high load threshold adjust mask.    
     
     
         19 . The method according to    claim 16   , wherein said second voltage is higher than said first voltage.  
     
     
         20 . The method according to    claim 16   , wherein said load threshold voltage comprises a P-type field effect transistor (PFET) load threshold voltage.  
     
     
         21 . A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine, to perform method steps for designing a circuit, said method steps comprising: 
 identifying paths in the circuit not satisfying preselected performance criteria, wherein the identified paths are initially designed to be coupled to a first power supply; and    redesigning the circuit such that identified paths are coupled to a second power supply having a higher voltage than the first power supply,    wherein the higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.    
     
     
         22 . A low-voltage-to-high voltage crossover circuit, comprising: 
 a plurality of devices, at least one of the devices having a first input and coupled to a first power supply for controlling an amount of current supplied to the circuit from the first power supply, and a second input for receiving a signal from at least one low power signal path, the low power signal path being coupled to a second power supply having a higher voltage than the first power supply; and    said at least one of the devices having an increased voltage threshold compared to others of the plurality of devices for minimizing an amount of current provided to the circuit from the first power supply.