Structure of capacitor and method for fabricating the same

Abstract

A structure of a lower electrode of a capacitor includes a first lower electrode, second lower electrodes formed at both sides of the first lower electrode and electrically connected to and higher than the first lower electrode, and a Hemispherical Grain-Silicon (HSG-Si) layer formed on a top surface of the first lower electrode and inside walls of the second lower electrodes.

What is claimed is:  
     
         1 . A structure of a lower electrode of a capacitor comprising: 
 a first lower electrode;    second lower electrodes formed at both sides of the first lower electrode and electrically connected to and higher than the first lower electrode; and    a Hemispherical Grain-Silicon (HSG-Si) layer formed on a top surface of the first lower electrode and inside walls of the second lower electrodes.    
     
     
         2 . The structure of    claim 1   , wherein the first lower electrode is a stack including a polysilicon layer and an amorphous silicon layer.  
     
     
         3 . The structure of    claim 1   , wherein the first lower electrode is a stack including a heavily doped amorphous silicon layer and a lightly doped amorphous silicon layer.  
     
     
         4 . The structure of    claim 1   , wherein each of the second lower electrodes includes an outside wall formed of a polysilicon layer and an inside wall formed of an amorphous silicon layer.  
     
     
         5 . The structure of    claim 1   , wherein each of the second lower electrodes includes an outside wall formed of heavily doped amorphous silicon and an inside wall formed of lightly doped amorphous silicon.  
     
     
         6 . The structure of    claim 1   , wherein only the inside wall of each of the second lower electrodes has grains of HSG-Si attached thereto.  
     
     
         7 . A method for fabricating a capacitor comprising the steps of: 
 forming an interlayer insulating film on a semiconductor substrate;    removing a portion of the interlayer insulating film to define a capacitor region;    depositing a first thin semiconductor layer and a second thin semiconductor layer;    depositing a planarizing insulating film on the second thin semiconductor layer;    etching back the planarizing insulating film, and the first and second thin semiconductor layers until a surface of the interlayer insulating film is exposed;    removing the planarizing insulating film and the interlayer insulating film to form a lower electrode; and    forming a HSG-Si layer on a surface of the second thin semiconductor layer.    
     
     
         8 . The method of    claim 7   , further including the steps of forming a dielectric film on the lower ecectrode and on the HSG-Si layer, and forming an upper electrode on the dielectric film.  
     
     
         9 . The method of    claim 7   , wherein the first thin semiconductor layer is formed of polysilicon and the second this semiconductor layer is formed of amorphous silicon.  
     
     
         10 . The method of    claim 7   , wherein the first thin semiconductor layer is formed of heavily doped amorphous silicon and the second thin semiconductor layer is formed of lightly doped amorphous silicon.  
     
     
         11 . The method of    claim 7   , wherein the first thin semiconductor layer is formed of amorphous silicon doped with a phosphorus concentration of at least 2.0×10 20  atoms/cm 3 , and wherein the second thin semiconductor layer is formed of amorphous silicon doped with a phosphorus concentration less than 2.0×10 20  atoms/cm 3 .  
     
     
         12 . The method of    claim 7   , wherein the step of forming the HSG-Si layer includes the steps of: 
 forming silicon seeds at approximately 570-620° C. using one of Si 2 H 6  gas and SiH 4  gas; and    annealing the capacitor.    
     
     
         13 . A method for fabricating a capacitor comprising the steps of: 
 forming an interlayer insulating film on a semiconductor substrate and having a contact hole;    depositing a conductive layer and a planarizing insulating film on the interlayer insulating film and the contact hole;    selectively removing the conductive layer and the planarizing, insulating film to leave the conductive layer and the planarizing insulating film only in a capacitor-forming region;    forming first semiconductor sidewalls at sides of the planarizing insulating film and connected to the conductive layer;    forming second semiconductor sidewalls at sides of the first semiconductor sidewalls;    removing the planarizing insulating film; and    forming a HSG-Si (Hemispherical Grain-Silicon) layer on surfaces of the first semiconductor sidewalls.    
     
     
         14 . The method of    claim 13   , wherein the first semiconductor sidewalls include amorphous silicon and the second semiconductor sidewalls include polysilicon.  
     
     
         15 . The method of    claim 13   , wherein the first semiconductor sidewalls include lightly doped amorphous silicon and the second semiconductor sidewalls include heavily doped amorphous silicon.  
     
     
         16 . A cylindrical lower electrode of a capacitor comprising: 
 a first bottom portion in contact with a substrate;    a second bottom portion on the first bottom portion and having different characteristics from the first bottom portion;    a cylinder wall having the same material as the second bottom portion on its inner side, and the same material as the first bottom portion on its outer side; and    a layer of HSG-Si (Hemispherical Grain-Silicon) formed on the inner side of the cylinder wall and the second bottom portion.    
     
     
         17 . The structure of    claim 16   , wherein the first bottom portion includes polysilicon and the second bottom portion includes amorphous silicon.  
     
     
         18 . The structure of    claim 16   , wheiein the first bottom portion includes heavily doped amorphous silicon and the second bottom portion includes lightly doped amorphous silicon.  
     
     
         19 . The structure of    claim 16   , wherein only the inner side of the cylinder wall and the second bottom portion have grains of HSG-Si attached thereto.  
     
     
         20 . The structure of    claim 16   , further including: 
 an impurity region in the substrate;    an insulating layer on the substrate and having a contact hole over the impurity region; and    a conductive plug filling the contact hole.