Wafer level packaging

Abstract

An integrated circuit package ( 50 ) may include an integrated circuit chip ( 22 ) having an integrated circuit ( 14 ). A lead frame ( 28 ) may be opposite the integrated circuit chip ( 22 ). The lead frame ( 28 ) may include at least one lead ( 30 ) electrically coupled to the integrated circuit ( 14 ) by a connector ( 42 ). The lead ( 30 ) may be within a periphery ( 32 ) of the integrated circuit chip ( 22 ). An encapsulant ( 44 ) may cover the integrated circuit ( 14 ), the connector ( 42 ) and a portion of the lead frame ( 28 ). A remaining portion of the lead frame ( 28 ) may be exposed from the encapsulant ( 44 ).

What is claimed is:  
     
         1 . An integrated circuit package, comprising: 
 an integrated circuit chip including an integrated circuit;    a lead frame opposite the integrated circuit chip;    the lead frame including at least one lead electrically coupled to the integrated circuit by a connector;    the lead within a periphery of the integrated circuit;    an encapsulant covering the integrated circuit, the connector, and a portion of the lead frame; and    a remaining portion of the lead frame exposed from the encapsulant.    
     
     
         2 . The integrated circuit package of    claim 1   , further comprising: 
 the lead frame including a plurality of leads;    each lead electrically coupled to the integrated circuit by a connector; and    each of the leads within the periphery of the integrated circuit chip.    
     
     
         3 . The integrated circuit package of    claim 1   , wherein a distal end of the lead is substantially parallel to the integrated circuit chip.  
     
     
         4 . The integrated circuit package of    claim 1   , wherein the connector is a wire bonded to the lead and to the integrated circuit.  
     
     
         5 . The integrated circuit package of    claim 1   , further comprising: 
 a bonding pad electrically coupled to the integrated circuit;    the bonding pad disposed proximate to a centerline of the integrated circuit; and    the connector being a wire bonded to the lead and to the bonding pad.    
     
     
         6 . The integrated circuit package of    claim 1   , wherein the lead is plated with palladium.  
     
     
         7 . A packaged wafer, comprising: 
 a wafer including a plurality of integrated circuit chips;    each integrated circuit chip including an integrated circuit;    a sheet of lead frames opposite the integrated circuit chips;    each lead frame including a lead electrically coupled to an opposing integrated circuit by a connector;    the lead within a periphery of an opposing integrated circuit;    an encapsulant covering the integrated circuits, the connectors, and a portion of each lead frame; and    a remaining portion of each lead frame exposed from the encapsulant.    
     
     
         8 . The packaged wafer of    claim 7   , wherein the sheet of lead frames is a unitary sheet of material.  
     
     
         9 . The packaged wafer of    claim 7   , the lead frames each further comprising: 
 a plurality of leads;    the leads each electrically coupled to the opposing integrated circuit by a connector; and    the leads each within the periphery of the opposing integrated circuit chip.    
     
     
         10 . The packaged wafer of    claim 7   , wherein a distal end of the each lead is substantially parallel to the opposing integrated circuit chip.  
     
     
         11 . The packaged wafer of    claim 7   , wherein each connector is a wire bonded to the lead and to the opposing integrated circuit.  
     
     
         12 . The packaged wafer of    claim 7   , further comprising: 
 a bonding pad electrically coupled to each of the integrated circuits;    the bonding pad disposed proximate to a centerline of the integrated circuit; and    the connector being a wire bonded to the lead and to the bonding pad.    
     
     
         13 . The packaged wafer of    claim 7   , wherein the lead is plated with palladium.  
     
     
         14 . A method of packaging integrated circuits, comprising the steps of: 
 disposing a sheet of lead frames opposite a plurality of integrated circuit chips each including an integrated circuit, each lead frame including a lead within a periphery of an opposing integrated circuit chip;    electrically coupling the lead of each lead frame to the opposing integrated circuit chip; and    encapsulating the integrated circuits and a portion of each lead frame, each encapsulated integrated circuit and opposing lead frame forming a discrete integrated circuit package.    
     
     
         15 . The method of    claim 14   , wherein the sheet of lead frames is a unitary sheet of material.  
     
     
         16 . The method of    claim 14   , wherein the step of electrically coupling the lead to an opposing integrated circuit comprises the step of bonding a wire to the lead and to a bonding pad of the opposed integrated circuit.  
     
     
         17 . The method of    claim 14   , further comprising the step of detaching the integrated circuit packages from one another.  
     
     
         18 . The method of    claim 14   , further comprising the step of mounting each lead frame to the opposing integrated circuit.  
     
     
         19 . The method of    claim 14   , further comprising the step of forming a polymide layer on the integrated circuit chips.  
     
     
         20 . The method of    claim 14   , further comprising the step of plating the lead with palladium.