Sacrificial spacer for integrated circuit transistors

Abstract

An improved processing technique results in a structure which maximizes contact area by eliminating a sidewall spacer used to form LDD regions. A sacrificial spacer is provided during processing to form the LDD regions, and is then removed prior to further processing of the device. A sidewall spacer is then formed in a self-aligned contact from a later deposited oxide layer used as an interlevel dielectric. This leaves only a single oxide sidewall spacer alongside the gate electrode, maximizing the surface area available for the self-aligned contact itself.

What is claimed is:  
     
         1 . A method for forming a semiconductor integrated device structure, comprising the steps of: 
 forming a gate electrode on a surface of a substrate;    implanting impurities into the substrate to form LDD regions adjacent the gate electrode;    forming temporary sidewalls alongside the gate electrode and on the substrate surface;    implanting impurities in to the substrate to form heavily doped source/drain regions on either side of the gate electrode and spaced therefrom; and    removing the temporary sidewalls.    
     
     
         2 . The method of    claim 1   , wherein the step of forming temporary sidewalls comprises the step of forming temporary sidewalls from a polymer material.  
     
     
         3 . The method of    claim 2   , wherein the polymer is parylene.  
     
     
         4 . The method of    claim 1   , wherein the sidewalls are formed by the steps of: 
 depositing a conformal layer over the device; and    anisotropically etching back the conformal layer.    
     
     
         5 . The method of    claim 4   , wherein the conformal layer has a thickness of approximately 1000-2000 angstroms.  
     
     
         6 . The method of    claim 4   , wherein the conformal layer comprises a polymer material which is removable by a process used to remove photoresist.  
     
     
         7 . The method of    claim 1   , further comprising the step of: 
 forming a conformal oxide layer over the gate electrode after the temporary sidewalls have been removed.    
     
     
         8 . The method of    claim 7   , further comprising the steps of: 
 defining a contact region over a source/drain region and a portion of the gate electrode; and    etching the conformal oxide within the contact region to expose a portion of the substrate surface, wherein a sidewall of oxide remains alongside the gate electrode within the contact region.    
     
     
         9 . The method of    claim 8   , wherein the conformal oxide is undoped.  
     
     
         10 . The method of    claim 8   , wherein the conformal oxide layer is deposited to a thickness of approximately 1000-2000 angstroms.  
     
     
         11 . The method of    claim 1   , wherein the gate electrode is formed by the steps of: 
 forming a gate oxide on the substrate surface;    forming a polycrystalline silicon layer on the gate oxide;    forming a protective oxide layer over the polycrystalline silicon layer; and    etching the gate oxide, polycrystalline silicon, and protective oxide layers to define the gate electrode.    
     
     
         12 . The method of    claim 11   , further comprising the step of: 
 forming a silicide layer on the polycrystalline silicon layer before forming the protective oxide layer.    
     
     
         13 . The method of    claim 1   , wherein the step of forming temporary sidewalls comprises the step of forming temporary sidewalls from amorphous carbon.  
     
     
         14 . The method of    claim 4   , wherein the conformal layer comprises a carbon material which is removable by a process used to remove photoresist.  
     
     
         15 . A method for forming transistors in a CMOS integrated circuit device, comprising the steps of: 
 forming first and second gate electrodes over first and second active regions of a substrate, respectively;    forming a first resist layer over the second active region;    implanting impurities into the first active region to form LDD regions adjacent the first gate electrode;    forming a first conformal temporary layer over the first active region, first gate electrode, and the first resist layer;    etching back the first temporary layer to form sidewalls alongside the first gate electrode;    implanting impurities into the first active region to form heavily doped source/drain regions space from the first gate electrode;    removing the first resist layer and the temporary sidewalls;    forming a second resist layer over the first active region;    implanting impurities into the second active region to form LDD regions adjacent the second gate electrode;    forming a second conformal temporary layer over the second active region, second gate electrode, and the second resist layer;    etching back the second temporary layer to form sidewalls alongside the second gate electrode;    implanting impurities into the second active region to form heavily doped source/drain regions space from the second gate electrode; and    removing the second resist layer and the sidewalls alongside the second gate electrode.    
     
     
         16 . The method of    claim 15   , further comprising the steps of: 
 depositing a conformal oxide layer over the gate electrodes and the active regions;    defining a contact region over at least one of the source/drain regions; and    etching the conformal oxide within the contact region to expose a portion of the substrate, wherein a sidewall is formed alongside a gate electrode within the contact region.    
     
     
         17 . The method of    claim 15   , wherein the first and second gate electrodes are formed by the steps of: 
 forming a gate oxide on the substrate surface;    forming a polycrystalline silicon layer on the gate oxide;    forming a protective oxide layer over the polycrystalline silicon layer; and    etching the gate oxide, polycrystalline silicon, and protective oxide layers to define the first and second gate electrodes.    
     
     
         18 . The method of    claim 17   , further comprising the step of: 
 forming a silicide layer on the polycrystalline silicon layer before forming the protective oxide layer.    
     
     
         19 . The method of    claim 15   , wherein the first and second polymer layers each have a thickness of approximately 1000-2000 angstroms.  
     
     
         20 . The method of    claim 15   , wherein the conformal temporary layers are formed from a polymer.  
     
     
         21 . The method of    claim 20   , wherein the conformal temporary layers are formed from parylene.  
     
     
         22 . The method of    claim 15   , wherein the conformal temporary layers are formed from amorphous carbon.  
     
     
         23 . A transistor structure in an integrated circuit device, comprising: 
 a substrate having a surface;    a gate electrode on the substrate surface;    lightly doped LDD regions in the substrate adjacent the gate electrode; and    heavily doped source/drain regions in the substrate adjacent the LDD regions;    wherein the gate electrode does not have sidewall spacers alongside vertical portions thereof.    
     
     
         24 . A transistor structure in an integrated circuit device, comprising: 
 a substrate having a surface;    a gate electrode on the substrate surface;    lightly doped LDD regions in the substrate adjacent the gate electrode; and    heavily doped source/drain regions in the substrate adjacent the LDD regions;    a conformal oxide layer of a selected thickness covering a portion of the gate electrode and a portion of one of the source/drain regions;    a sidewall oxide region alongside a vertical sidewall of the gate electrode, formed from the same material as the conformal oxide layer, and having a thickness substantially the same as the selected thickness.    
     
     
         25 . The structure of    claim 24   , wherein the gate electrode comprises: 
 a gate oxide layer on the substrate surface;    a doped polycrystalline silicon layer on the gate oxide layer; and    a protective oxide layer over the polycrystalline silicon layer.    
     
     
         26 . The structure of    claim 21   , further comprising: 
 a silicide layer between the polycrystalline silicon layer and the protective oxide layer.