Lead-less semiconductor device with improved electrode pattern structure

Abstract

A semiconductor device comprises: an insulating substrate have a first main face which is sealed with a sealing material; at least a set of input and output electrode patterns provided on the first main face, and the input and output electrode patterns being separated from each other; at least a ground electrode pattern having a ground potential, and the ground electrode pattern being separated from the input and output electrode patterns; and at least an electrically conductive pattern extending over an inter-region between the input and output electrode patterns, and the electrically conductive pattern being separated from the input and output electrode patterns, and the electrically conductive pattern being electrically connected to the ground electrode pattern, so that the electrically conductive pattern has a ground potential.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an insulating substrate have a first main face which is sealed with a sealing material;    at least a set of input and output electrode patterns provided on said first main face, and said input and output electrode patterns being separated from each other;    at least a ground electrode pattern having a ground potential, and said ground electrode pattern being separated from said input and output electrode patterns; and    at least an electrically conductive pattern extending over an inter-region between said input and output electrode patterns, and said electrically conductive pattern being separated from said input and output electrode patterns, and said electrically conductive pattern being electrically connected to said ground electrode pattern, so that said electrically conductive pattern has a ground potential.    
     
     
         2 . The device as claimed in    claim 1   , wherein said electrically conductive pattern extends from said ground electrode pattern, so that said electrically conductive pattern is unitary formed with said ground electrode pattern.  
     
     
         3 . The device as claimed in    claim 1   , wherein one of said ground electrode pattern is provided for a single set of said input and output electrode patterns, and said electrically conductive pattern extends from said one ground electrode pattern.  
     
     
         4 . The device as claimed in    claim 1   , wherein a plurality of said ground electrode pattern is provided for a single set of said input and output electrode patterns, and said electrically conductive pattern extends from one of said plural ground electrode patterns.  
     
     
         5 . The device as claimed in    claim 1   , wherein each of said plural ground electrode patterns is provided for each of plural sets of said input and output electrode patterns, and each of said plural electrically conductive patterns extends from each of said plural ground electrode patterns.  
     
     
         6 . The device as claimed in    claim 1   , wherein a plurality of said ground electrode pattern is provided for each of plural sets of said input and output electrode patterns, and said electrically conductive pattern extends from one of said plural ground electrode patterns for each set of said input and output electrode patterns.  
     
     
         7 . The device as claimed in    claim 1   , further comprising: a plurality of through holes filled with an electrically conductive material, and said through holes being in contact with said electrically conductive pattern and being positioned between via holes connected with said input and output electrode patterns.  
     
     
         8 . The device as claimed in    claim 1   , wherein one of said input and output electrode patterns comprises a chip mounting electrode, on which a semiconductor chip is mounted.  
     
     
         9 . The device as claimed in    claim 1   , wherein said ground electrode pattern comprises a chip mounting electrode, on which a semiconductor chip is mounted.  
     
     
         10 . The device as claimed in    claim 1   , wherein said insulating substrate comprises a ceramic base substrate.  
     
     
         11 . A semiconductor device comprising: 
 an insulating substrate have a first main face which is sealed with a sealing material;    at least a set of input and output electrode patterns provided on said first main face, and said input and output electrode patterns being separated from each other;    at least a ground electrode pattern having a ground potential, and said ground electrode pattern being provided on an inter-region between said input and output electrode patterns and separated from said input and output electrode patterns; and    a semiconductor chip mounted on said ground electrode pattern.    
     
     
         12 . The device as claimed in    claim 10   , wherein said semiconductor chip has a first terminal connected to said input electrode pattern, a second terminal connected to said output electrode pattern, and a third terminal connected to an extending pattern which extends from said ground electrode pattern.  
     
     
         13 . The device as claimed in    claim 11   , wherein said insulating substrate comprises a ceramic base substrate.  
     
     
         14 . An electrode pattern structure on a first main face of an insulating substrate, said structure comprising: 
 at least a set of input and output electrode patterns being separated from each other;    at least a ground electrode pattern having a ground potential and being separated from said input and output electrode patterns; and    at least an electrically conductive pattern extending over an inter-region between said input and output electrode patters, and said electrically conductive pattern being separated from said input and output electrode patterns, and said electrically conductive pattern being electrically connected to said ground electrode pattern, so that said electrically conductive pattern has a ground potential.    
     
     
         15 . The structure as claimed in    claim 14   , wherein said electrically conductive pattern extends from said ground electrode pattern, so that said electrically conductive pattern is unitary formed with said ground electrode pattern.  
     
     
         16 . The structure as claimed in    claim 14   , wherein one of said ground electrode pattern is provided for a single set of said input and output electrode patterns, and said electrically conductive pattern extends from said one ground electrode pattern.  
     
     
         17 . The structure as claimed in    claim 14   , wherein a plurality of said ground electrode pattern is provided for a single set of said input and output electrode patterns, and said electrically conductive pattern extends from one of said plural ground electrode patterns.  
     
     
         18 . The structure as claimed in    claim 14   , wherein each of said plural ground electrode patterns is provided for each of plural sets of said input and output electrode patterns, and each of said plural electrically conductive patterns extends from each of said plural ground electrode patterns.  
     
     
         19 . The structure as claimed in    claim 14   , wherein a plurality of said ground electrode pattern is provided for each of plural sets of said input and output electrode patterns, and said electrically conductive pattern extends from one of said plural ground electrode patterns for each set of said input and output electrode patterns.  
     
     
         20 . The structure as claimed in    claim 14   , wherein one of said input and output electrode patterns comprises a chip mounting electrode, on which a semiconductor chip is mounted.  
     
     
         21 . The structure as claimed in    claim 14   , wherein said ground electrode pattern comprises a chip mounting electrode, on which a semiconductor chip is mounted.  
     
     
         22 . An electrode pattern structure on a first main face of an insulating substrate, said structure comprising: 
 at least a set of input and output electrode patterns being separated from each other; and    at least a ground electrode pattern having a ground potential, and said ground electrode pattern being provided on an inter-region between said input and output electrode patterns and separated from said input and output electrode patterns.