Storage media being readable by a computer, and a method for designing a semiconductor integrated circuit device

Abstract

The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation=Act n ) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.

What is claimed is:  
     
         1 . A method for designing a semiconductor integrated circuit device using logic cells used when constituting at least a part of the semiconductor integrated circuit device by the unit of logic cell, comprising the steps of: 
 preparing a standard delay file by calculating propagation delays with respect to logic cells that constitute said semiconductor integrated circuit device, on the basis of a delay library that stores an input signal transition time of said logic cells; an output capacitance of said logic cells; parameters used when calculating aged changes of a delay time of logic cells in the case where said input signal transition time and said output capacitance are given; an output signal rise transition time and an output signal fall transition time; and an output signal rise propagation delay and output signal fall transition time, and    obtaining the total propagation delay of the critical path in said semiconductor integrated circuit device by summing up a value of a propagation delay of logic cells that constitute said critical path, along with said standard delay file.    
     
     
         2 . A method for designing a semiconductor integrated circuit device according to    claim 1   , wherein said delay library includes a parameter of temperature changes and power supply voltage fluctuations, and said parameter is handled as a total constant that need not be selected separately for each of logic cells and load conditions.  
     
     
         3 . A method for designing at least a part of a semiconductor integrated circuit device by combining a plurality of logic cells, comprising the steps of: 
 obtaining a reliability factor in respective logic cells that constitute at least a part of said semiconductor integrated circuit device; and    reducing the reliability factor with respect to a logic cell having the first reliability factor of said respective logic cells so that said reliability factor is caused to reside between the second reliability factor, which is lower than said predetermined first reliability factor, and the third reliability factor, which is lower than said second reliability factor.    
     
     
         4 . A method for designing a semiconductor integrated circuit device according to    claim 3   , further comprising a step of increasing the reliability factor with respect to logic cells, which do not meet the reliability factor requirement, of said respective logic cells so that said reliability factor is caused to reside between said predetermined second reliability factor and said third reliability factor.  
     
     
         5 . A method for designing a semiconductor integrated circuit device according to    claim 4   , wherein, where tp 0  is the fresh delay quantity and Δtp is an aged delay quantity, said reliability factor RF is expressed to be: 
 RF=1/(Sensitivity×Degradation)  
 Degradation=Δtp/tp 0  of the respective logic cells  
 Sensitivity=Δtp/tp 0  of the critical path of a semiconductor integrated circuit device)/(Δtp/tp 0  of the respective logic cells).  
 
     
     
         6 . A method for designing a semiconductor integrated circuit device according to    claim 5   , wherein said reliability factor is variable by changing an input signal transition time of said respective logic cells; 
 when changing said input signal transition time; 
 (1) the current drivability of the preceding cell is changed,  
 (2) the capacitive load of the intervening part between the preceding cell and the present cell is changed as follows; 
 (a) the resistance load and capacitive load at the input side are changed by changing the path of said intervening part, or  
 (b) buffers are added/inserted or removed between the preceding cell and the present cell.  
 
   
     
     
         7 . A method for designing a semiconductor integrated circuit device according to    claim 5   , wherein said reliability factor is variable by changing an output signal transition time of said respective logic cells; 
 when changing the output signal transition time; 
 (1) the current drivability of the present cell is changed,  
 (2) the capacitive load of the intervening part between the present cell and the following cell is changed as follows; 
 (a) the resistance load and capacitive load are changed by changing the path of the intervening part; or  
 (b) buffers are added/inserted or removed between the present cell and the following cell.  
 
   
     
     
         8 . A method for designing a semiconductor integrated circuit device according to    claim 4   , wherein said second reliability factor and said third reliability factor are established, depending on the circuit operating time and permissible degradation value of said semiconductor integrated circuit device.