Semiconductor device and method of driving the same

Abstract

To provide a semiconductor device and a driving method of the same that is capable of enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long. The semiconductor device having an amplifying transistor and a biasing transistor and the driving method thereof, wherein an electric discharging transistor is provided and pre-discharge is performed.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an amplifying transistor;    a biasing transistor;    an amplifying side power source line;    a biasing side power source line;    a bias signal line;    an electric discharging transistor; and    an electric discharging power source line, 
 wherein a drain terminal of the amplifying transistor is connected to the amplifying side power source line, a source terminal of the biasing transistor is connected to the biasing side power source line, a source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor, a gate terminal of the biasing transistor is connected to the bias signal line, a gate terminal of the amplifying transistor serves as an input terminal, and a source terminal of the amplifying transistor serves as an output terminal, and  
 wherein one of the output terminal and the electric discharging power source line is connected to a source terminal of the electric discharging transistor while the other thereof is connected to a drain terminal of the electric discharging transistor.  
   
     
     
         2 . A device according to    claim 1    further comprising a load capacitance wherein one terminal of the load capacitance is connected to the output terminal, and the other terminal of the load capacitance is connected to a load capacitance power source line.  
     
     
         3 . A device according to    claim 1   , wherein the electric discharging power source line is connected to the biasing side power source line.  
     
     
         4 . A device according to    claim 1    further comprising at least one selecting switch for controlling an electric current flowing to the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         5 . A device according to    claim 1    wherein an absolute value of a voltage between a gate and a source of the biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the biasing transistor into a conductive state.  
     
     
         6 . A device according to    claim 1   , wherein a photoelectric conversion element is connected to the input terminal.  
     
     
         7 . A device according to    claim 1   , wherein a signal generated by a photoelectric conversion element is fed to the input terminal.  
     
     
         8 . A device according to    claim 1   , wherein when the semiconductor device has a plurality of biasing transistors, an absolute value of a voltage between a gate and a source of the plurality of biasing transistors is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the entire plurality of biasing transistors into a conductive state.  
     
     
         9 . A device according to    claim 1   , wherein the amplifying transistor, the biasing transistor, and the electric discharging transistor are transistors having the same polarity.  
     
     
         10 . A scanner, which uses the semiconductor device according to    claim 1   .  
     
     
         11 . A digital still camera, which uses the semiconductor device according to    claim 1   .  
     
     
         12 . An X-ray camera, which uses the semiconductor device according to    claim 1   .  
     
     
         13 . A portable information terminal, which uses the semiconductor device according to    claim 1   .  
     
     
         14 . A computer, which uses the semiconductor device according to    claim 1   .  
     
     
         15 . A device according to    claim 2   , wherein at least 2 lines from among the electric discharging power source line, the load capacitance power source line, and the biasing side power source line are connected together.  
     
     
         16 . A device according to    claim 2   , wherein the load capacitance power source line is connected to the amplifying side power source line.  
     
     
         17 . A device according to    claim 2    further comprising at least one selecting switch for controlling an electric current flowing to the load capacitance or the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         18 . A device according to    claim 17   , wherein the selecting switch has at least one of an N channel transistor or a P channel transistor.  
     
     
         19 . A device according to    claim 6   , wherein the photoelectric conversion element is either an X-ray sensor or an infrared sensor.  
     
     
         20 . A device according to    claim 6   , wherein the photoelectric conversion element is any one of a photo diode, a Schottky diode, an avalanche diode, or a photo conductor.  
     
     
         21 . A device according to    claim 20   , wherein the photo diode is one of a type incorporating a PN type, a PIN type, or an NPN embedded type.  
     
     
         22 . A device according to claims  6  further comprising a resetting transistor, and a source terminal or a drain terminal of the resetting transistor is connected to the photoelectric conversion element.  
     
     
         23 . A semiconductor device comprising: 
 an amplifying transistor;    a biasing transistor;    an amplifying side power source line;    a biasing side power source line;    a signal generating device; and    a bias signal line, 
 wherein a drain terminal of the amplifying transistor is connected to the amplifying side power source line, a source terminal of the biasing transistor is connected to the biasing side power source line, a source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor, a gate terminal of the biasing transistor is connected to the bias signal line, a gate terminal of the amplifying transistor serves as an input terminal, and a source terminal of the amplifying transistor serves as an output terminal, and  
 wherein the signal generating device is connected to the bias signal line for performing the operation of making the electric potential of the biasing side power source line close to the electric potential of the amplifying side power source line.  
   
     
     
         24 . A device according to    claim 23    further comprising a load capacitance wherein one terminal of the load capacitance is connected to the output terminal, and the other terminal of the load capacitance is connected to a load capacitance power source line.  
     
     
         25 . A device according to    claim 23    further comprising at least one selecting switch for controlling an electric current flowing to the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         26 . A device according to    claim 23    wherein an absolute value of a voltage between a gate and a source of the biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the biasing transistor into a conductive state.  
     
     
         27 . A device according to    claim 23   , wherein a photoelectric conversion element is connected to the input terminal.  
     
     
         28 . A device according to    claim 23   , wherein a signal generated by a photoelectric conversion element is fed to the input terminal.  
     
     
         29 . A device according to    claim 23   , wherein when the semiconductor device has a plurality of biasing transistors, an absolute value of a voltage between a gate and a source of the plurality of biasing transistors is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the entire plurality of biasing transistors into a conductive state.  
     
     
         30 . A scanner, which uses the semiconductor device according to    claim 23   .  
     
     
         31 . A digital still camera, which uses the semiconductor device according to    claim 23   .  
     
     
         32 . An X-ray camera, which uses the semiconductor device according to    claim 23   .  
     
     
         33 . A portable information terminal, which uses the semiconductor device according to    claim 23   .  
     
     
         34 . A computer, which uses the semiconductor device according to    claim 23   .  
     
     
         35 . A driving method of a semiconductor device having an amplifying transistor, a biasing transistor, an amplifying side power source line, a biasing side power source line, and a bias signal line, 
 wherein a drain terminal of the amplifying transistor is connected to the amplifying side power source line, a source terminal of the biasing transistor is connected to the biasing side power source line, a source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor,    wherein a gate terminal of the biasing transistor is connected to the bias signal line, a gate terminal of the amplifying transistor serves as an input terminal, and a source terminal of the amplifying transistor serves as an output terminal, and    wherein the driving method outputs a signal after performing a pre-discharge.    
     
     
         36 . A method according to    claim 35    further comprising a load capacitance wherein one terminal of the load capacitance is connected to the output terminal, and the other terminal of the load capacitance is connected to a load capacitance power source line.  
     
     
         37 . A method according to    claim 35   , wherein the semiconductor device has at least one selecting switch for controlling an electric current flowing to the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         38 . A method according to    claim 35   , wherein an absolute value of a voltage between a gate and a source of the biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the biasing transistor into a conductive state.  
     
     
         39 . A method according to    claim 35    further comprising a photoelectric conversion element connected to the input terminal.  
     
     
         40 . A method according to    claim 35   , wherein a signal generated by a photoelectric conversion element is fed to the input terminal.  
     
     
         41 . A method according to    claim 35   , wherein when the semiconductor device has a plurality of biasing transistors, an absolute value of a voltage between a gate and a source of the plurality of biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the entire plurality of biasing transistors into a conductive state.  
     
     
         42 . A method according to    claim 36   , wherein at least 2 lines from among the electric discharging power source line, the load capacitance power source line, and the biasing side power source line are to be connected together.  
     
     
         43 . A method according to    claim 36   , wherein the load capacitance power source line is connected to the amplifying side power source line.  
     
     
         44 . A method according claims  36 , wherein the semiconductor device has at least one selecting switch for controlling an electric current flowing to the load capacitance or the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         45 . A method according to    claim 44   , wherein the selecting switch has at least one of an N channel transistor or a P channel transistor.  
     
     
         46 . A method according to    claim 39   , wherein the photoelectric conversion element is either an X-ray sensor or an infrared sensor.  
     
     
         47 . A method according to    claim 39   , wherein the photoelectric conversion element is any one of a photo diode, a Schottky diode, an avalanche diode, or a photo conductor.  
     
     
         48 . A method according to    claim 47   , wherein the photo diode is any one of a type incorporating a PN type, a PIN type, or an NPN embedded type.  
     
     
         49 . A method according to    claim 39   , wherein the semiconductor device has a resetting transistor, and the resetting transistor resets the photoelectric conversion element.  
     
     
         50 . A driving method of a semiconductor device having an amplifying transistor, a biasing transistor, an amplifying side power source line, a biasing side power source line, and a bias signal line, 
 wherein a drain terminal of the amplifying transistor is connected to the amplifying side power source line, a source terminal of the biasing transistor is connected to the biasing side power source line, a source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor, a gate terminal of the biasing transistor is connected to the bias signal line, a gate terminal of the amplifying transistor serves as an input terminal, and a source terminal of the amplifying transistor serves as an output terminal, and    wherein the driving method outputs a signal after performing a pre-discharge by making an electric potential of the biasing side power source line close to an electric potential of the amplifying side power source line.    
     
     
         51 . A method according to    claim 50    further comprising a load capacitance wherein one terminal of the load capacitance is connected to the output terminal, and the other terminal of the load capacitance is connected to a load capacitance power source line.  
     
     
         52 . A method according to    claim 50   , wherein the semiconductor device has at least one selecting switch for controlling an electric current flowing to the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         53 . A method according to    claim 50   , wherein an absolute value of a voltage between a gate and a source of the biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the biasing transistor into a conductive state.  
     
     
         54 . A method according to    claim 50    further comprising a photoelectric conversion element connected to the input terminal.  
     
     
         55 . A method according to    claim 50   , wherein a signal generated by a photoelectric conversion element is fed to the input terminal.  
     
     
         56 . A method according to    claim 50   , wherein when the semiconductor device has a plurality of biasing transistors, an absolute value of a voltage between a gate and a source of the plurality of biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the entire plurality of biasing transistors into a conductive state.  
     
     
         57 . A driving method of a semiconductor device having an amplifying transistor, a biasing transistor, an amplifying side power source line, a biasing side power source line, and a bias signal line, an electric discharging transistor, and an electric discharging power source line, 
 wherein a drain terminal of the amplifying transistor is connected to the amplifying side power source line, a source terminal of the biasing transistor is connected to the biasing side power source line, a source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor, a gate terminal of the biasing transistor is connected to the bias signal line, a gate terminal of the amplifying transistor serves as an input terminal, a source terminal of the amplifying transistor serves as an output terminal, one of the output terminal and the electric discharging power source line is connected to a source terminal of the electric discharging transistor while the other thereof is connected to a drain terminal of the electric discharging transistor, and    wherein the driving method outputs a signal after performing a pre-discharge by making the electric discharging transistor into a conductive state.    
     
     
         58 . A method according to    claim 57   , wherein a value of an electric potential of the electric discharging power source line takes a value that is between an electric potential of the bias signal line and an electric potential of the biasing side power source line.  
     
     
         59 . A method according to    claim 57    further comprising a load capacitance wherein one terminal of the load capacitance is connected to the output terminal, and the other terminal of the load capacitance is connected to a load capacitance power source line.  
     
     
         60 . A method according to    claim 57   , wherein the electric discharging power source line and the biasing side power source line are to be connected together.  
     
     
         61 . A method according to    claim 57   , wherein the semiconductor device has at least one selecting switch for controlling an electric current flowing to the output terminal from the amplifying side power source line or from the biasing side power source line.  
     
     
         62 . A method according to    claim 57   , wherein an absolute value of a voltage between a gate and a source of the biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the biasing transistor into a conductive state.  
     
     
         63 . A method according to    claim 57    further comprising a photoelectric conversion element connected to the input terminal.  
     
     
         64 . A method according to    claim 57   , wherein a signal generated by a photoelectric conversion element is fed to the input terminal.  
     
     
         65 . A method according to    claim 57   , wherein when the semiconductor device has a plurality of biasing transistors, an absolute value of a voltage between a gate and a source of the plurality of biasing transistor is equivalent to a minimum value of an absolute value of a voltage between a gate and a source that is necessary for making the entire plurality of biasing transistors into a conductive state.  
     
     
         66 . A method according to claims  57 , wherein the amplifying transistor, the biasing transistor, and the electric discharging transistor are transistors having the same polarity.