Semiconductor device with multiple emitter contact plugs

Abstract

A semiconductor device, such as a BICMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. The contact plugs are partially embedded in the emitter electrode in order to prevent of reduction of the current amplification factor of the bipolar transistor.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device which includes a bipolar transistor having at least an emitter region, comprising the steps of: 
 forming an emitter electrode on said emitter region;    forming an insulating layer on said emitter electrode;    forming a plurality of contact holes in said insulating layer;    embedding a plurality of contact plugs in the contact holes; and    forming a wiring pattern on said insulating layer.    
     
     
         2 . A method as claimed in    claim 1   , wherein: 
 said contact plugs are partially embedded in said emitter electrode.    
     
     
         3 . A method as claimed in    claim 1   , wherein: 
 said bipolar transistor has a predetermined current amplification factor, and    said contact plugs are formed in order to prevent reduction of the current amplification factor.    
     
     
         4 . A method as claimed in    claim 1   , wherein: 
 each of said contact plugs is formed by tungsten,    said emitter electrode is formed by a polysilicon, and    said wiring pattern is formed by aluminum.    
     
     
         5 . A method as claimed in    claim 1   , further comprising the steps of: 
 forming an epitaxial layer on a silicon substrate; and    forming said emitter region in said epitaxial layer.    
     
     
         6 . A method of manufacturing a BiCMOS semiconductor device which includes a CMOS transistor which has at least source and drain regions and a bipolar transistor which has at least an emitter electrode and which is arranged adjacent to said CMOS transistor, comprising the steps of: 
 forming a first insulating layer on said CMOS transistor;    forming a second insulating layer on said bipolar transistor;    forming a first contact hole in said first insulating layer;    forming a plurality of contact holes in said second insulating layer;    embedding a first contact plug in said first contact hole;    embedding second contact plugs in said second contact holes;    forming a first wiring pattern on said first insulating layer; and    forming a second wiring pattern on said second insulating layer.    
     
     
         7 . A method claimed in    claim 6   , wherein: 
 the height of said second insulating layer is smaller than that of said first insulating layer.    
     
     
         8 . A method claimed in    claim 6   , wherein: 
 the height of said second contact plug is smaller than that of said first contact plug.    
     
     
         9 . A method as claimed in    claim 6   , wherein: 
 said first contact plug contacts with a surface of either one of said source and drain regions while said second contact plugs are partially embedded in said emitter electrode.    
     
     
         10 . A method as claimed in    claim 6   , wherein: 
 said bipolar transistor has a predetermined current amplification factor, and    said second contact plugs are formed in order to prevent of the current amplification factor.    
     
     
         11 . A method of making a semiconductor device that includes a bipolar transistor formation region having an emitter diffusion region and a CMOS transistor formation region having a source/drain diffusion region, the method comprising the steps of: 
 forming an interlayer insulator over the emitter diffusion region and the source/drain diffusion region, the interlayer insulator being thicker over the source/drain diffusion region than over the emitter diffusion region;    forming a first contact plug that extends through the interlayer insulator into contact with the source/drain diffusion region;    forming plural second contact plugs that extend through the interlayer insulator into contact with the emitter diffusion region, the plural second contact plugs being directly over the emitter diffusion region so that the plural second contact plugs overlap the emitter diffusion region;    forming a first wiring layer over the interlayer insulator over the source/drain diffusion region, the first wiring layer contacting the first contact plug; and    forming a second wiring layer over the interlayer insulator over the emitter diffusion region, the second wiring layer contacting the plural second contact plugs.    
     
     
         12 . The method of    claim 1   , wherein the plurality of contact holes are formed directly over the emitter region so that the plurality of contact plugs overlap the emitter region.  
     
     
         13 . The method of    claim 6   , wherein the plurality of second contact holes are formed directly over the emitter region so that the second contact plugs overlap the emitter region.