Via code Mask ROM

Abstract

The present invention provides a Via Code Mask read-only memory comprising an array of transistors, and a plurality of bit lines and word lines, wherein the transistors in each row of the array are connected in series by connection of a drain/source of one transistor with a drain/source of another transistor. Both ends of the series of the transistors in each row of the array are connected to a supply voltage together. Each one of the bit lines is selectively connected to drain(s)/source(s) of one or more transistors in one corresponding column. Each one of the word lines connects together gates of the transistors in one corresponding row.

What is claimed is:  
     
         1 . A Via Code Mask read-only memory, comprising: 
 an array of transistors, wherein by connection of a drain/source of one transistor with a drain/source of another transistor, the transistors in each row of the array are connected in series, and both ends of the series of the transistors in each row of the array are connected to a supply voltage together;    a plurality of bit lines, wherein each one of the bit lines is selectively connected to drain(s)/source(s) of one or more transistors in one corresponding column; and    a plurality of word lines, wherein each one of the word lines connects together gates of the transistors in one corresponding row.    
     
     
         2 . The Via Code Mask read-only memory as claimed in    claim 1   , wherein the supply voltage is a ground voltage.  
     
     
         3 . The Via Code Mask read-only memory as claimed in    claim 1   , wherein the connections between the bit lines and drain(s)/source(s) of the transistors are carried out by Via Code.  
     
     
         4 . A Via Code Mask read-only memory, comprising: 
 an array of memory cells comprising: 
 an array of transistors, wherein by connection of a drain/source of one transistor with a drain/source of another transistor, the transistors in each row of the array are connected in series, and both ends of the series of the transistors in each row of the array are connected to a supply voltage together;  
 a plurality of bit lines, wherein each one of the bit lines is selectively connected to drain(s)/source(s) of one or more transistors in one corresponding column; and  
 a plurality of word lines, wherein each one of the word lines connects together gates of the transistors in one corresponding row;  
   a row address decoder receiving a row address and accordingly turning on all the transistors in one of the columns of the array through one of the corresponding word lines; and    a column address decoder receiving a column address, selecting one of the bit lines accordingly and outputting a voltage on the selected bit line.    
     
     
         5 . The Via Code Mask read-only memory as claimed in    claim 4   , wherein the supply voltage is a ground voltage.  
     
     
         6 . The Via Code Mask read-only memory as claimed in    claim 4   , wherein the connections between the bit lines and drain(s)/source(s) of the transistors are carried out by Via Code.