Semiconductor device and alignment apparatus and alignment method for same

Abstract

In a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer, the first alignment marks and second alignment marks are disposed so as to be approximately as close to each other as a diffraction grating distance X.

What is claimed is:  
     
         1 . A semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer being different from said first layer, wherein said first alignment marks and said second alignment marks are disposed so as to be at a distance from each other that is approximately a diffraction grating distance.  
     
     
         2 . An alignment apparatus for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on said second layer, said alignment apparatus comprising: 
 a first detection means for determining the position of said second alignment marks with respect to said first alignment marks;    a second detection means for detecting the skew between the position of said second alignment marks and the position of said first alignment marks that are detected by said first detection means;    a third detection means for detecting whether or not the distribution of the skew detected by said second detection means is within a prescribed value; and    an alignment execution means for performing alignment by selecting said second alignment marks in the case in which said third detection means detects that said skew distribution is within said prescribed value.    
     
     
         3 . An alignment apparatus according to    claim 2   , wherein said prescribed value is a distribution of 3σ.  
     
     
         4 . An alignment apparatus for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer, said alignment apparatus comprising: 
 a first detection means for detecting the position of said second alignment marks with respect to said first alignment marks;    a second detection means for detecting the skew between the position of said second alignment marks and the position of said first alignment marks that are detected by said first detection means;    a third detection means for detecting whether or not the distribution of skew detected by said second detection means is within a prescribed value;    a fourth detection means for correcting a linear error component such as position offset of said second alignment marks with respect to said first alignment marks, and detecting the residual error thereof;    a fifth detection means for detecting whether or not said residual error detected by said fourth detection means is within a prescribed value; and    an alignment execution means for performing alignment by selecting said second alignment marks in the case in which not only does said third detection means detect that said skew distribution is within its prescribed value, but also said fifth detection means detects that said residual error is within its prescribed value.    
     
     
         5 . An alignment apparatus according to    claim 2   , wherein said second alignment marks are formed on a layer that is disposed above the layer on which said first alignment marks are formed.  
     
     
         6 . An alignment apparatus according to    claim 2   , wherein said first alignment marks and said second alignment marks are disposed so as to be approximately as close to each other as a diffraction grating distance.  
     
     
         7 . An alignment method for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer being different from said first layer, said alignment apparatus comprising: 
 a first step of determining the position coordinates of said second alignment marks with respect to said first alignment marks;    a second step of detecting the skew between the position of said second alignment marks and the position of said first alignment marks that are detected at the first step;    a third step of detecting whether or not the distribution of said skew detected at said second step is within a prescribed value;    a fourth step of performing alignment by selecting said second alignment marks, when the distribution of said skew is detected as being within said prescribed value in the third step.    
     
     
         8 . An alignment method for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer being different from said first layer, said alignment apparatus comprising: 
 a first step of determining the position coordinates of said second alignment marks with respect to said first alignment marks;    a second step of detecting the skew between the position of said second alignment marks and the position of said first alignment marks that are detected at the first step;    a third step of detecting whether or not the distribution of said skew detected at said second step is within a prescribed value;    a fourth step of correcting a linear error component such as the position offset of said second alignment marks with respect to the first alignment marks, based on said position coordinates detected at said first step, and detecting the residual error thereof;    a fifth step of determining whether or not said residual error detected at said fourth step is within a prescribed value; and    a sixth step of performing alignment by selecting said second alignment marks, if not only at said third step the distribution of said skew is detected as being within its prescribed value but also at said fifth step said residual error is detected as being within its prescribed value.