Semiconductor integrated circuit device and method of manufacturing the same

Abstract

In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device, comprising: 
 memory cells each comprised of a memory cell selection MISFET and an information storage capacitive. element connected in series with said memory cell selection MISFET;    a first interconnection formed over said memory cell selection MISFET;    a first insulating film formed over said first interconnection;    a second insulating film formed over said information storage capacitive element;    a second interconnection formed over said second insulating film;    a first conductive layer formed within a first through hole defined in said second insulating film and said first insulating film placed in a layer therebelow, said first conductive layer connecting said second interconnection and said first interconnection;    a third insulating film formed over said second interconnection;    a feeding interconnection for supplying a predetermined potential to an upper electrode of said information-storage capacitive element formed over said third insulating film; and    a second conductive layer formed within a second through hole defined in said third insulating film and said second insulating film placed in a layer therebelow, said second conductive layer connecting said upper electrode and said feeding interconnection;    wherein said information storage capacitive element is formed inside each groove defined in said first insulating film.    
     
     
         2 . The semiconductor integrated circuit device according to    claim 1   , wherein said third insulating film formed over said second interconnection includes an insulating film formed by a high-density plasma CVD method, and said second insulating film formed over said information storage capacitive element excludes the insulating film formed by the high-density plasma CVD method.  
     
     
         3 . The semiconductor integrated circuit device according to    claim 1   , wherein a lower electrode of said each information storage capacitive element is disposed along a side wall of said each groove.  
     
     
         4 . The semiconductor integrated circuit device according to    claim 1   , wherein said first and second interconnections are disposed in a peripheral circuit region.  
     
     
         5 . The semiconductor integrated circuit device according to    claim 4   , wherein each bit line formed in the same process-step as the first interconnection of the peripheral circuit is formed below said each information storage capacitive element.  
     
     
         6 . A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 
 forming memory cell selection MISFETs in a memory array region on a main surface of a semiconductor substrate and forming MISFETs for a peripheral circuit in a peripheral circuit region;    forming a first interconnection over the main surface of said semiconductor substrate with the MISFETs formed therein;    forming a first insulating film over said first interconnection;    defining grooves in said first insulating film in said memory array region;    forming a first conductive film over said first insulating film including the interior of said grooves and forming a lower electrode of an information storage capacitive element inside said each groove;    forming a second conductive film over said lower electrode with a capacitive insulating film interposed therebetween, and pattering said second conductive film to thereby form each upper electrode of said information storage capacitive element;    forming a second insulating film over said each information storage capacitive element;    defining a first through hole in an insulating film including said second insulating film and said first insulating film placed in a layer therebelow; a step for forming a third conductive film over said second insulating film and patterning said third conductive film to thereby form a second interconnection electrically connected to said first interconnection via said first through hole;    forming a third insulating film over said sd'cond interconnection;    defining a second through hole in said third insulating film provided over said each information storage capacitive element and defining a third through hole in said third insulating film provided over said second interconnection; and    forming a fourth conductive film over said third insulating film and patterning said fourth conductive film to thereby form a feeding interconnection layer electrically connected to the upper electrode of said each information storage capacitive element via said second through hole, and a third interconnection electrically connected to said second interconnection via said third through hole.    
     
     
         7 . The method according to    claim 6   , wherein said step of forming the third insulating film over the second interconnection includes a step of forming an insulating film by a high-density plasma CVD method, and said step of forming the second insulating film over said information storage capacitive element excludes the step of forming the insulating film by the high-density plasma CVD method.  
     
     
         8 . The method according to    claim 7   , wherein said step of forming the insulating film by the high-density plasma CVD method is a step of forming a silicon oxide film be a high-density plasma CVD method using a source gas containing monosilane, oxygen and an inert gas.  
     
     
         9 . The method according to    claim 7   , wherein said step of forming the third insulating film over the second interconnection further includes a step of forming a fourth insulating film over the insulating film formed by the high-density plasma CVD method, and a step of flattening said fourth insulating film over the surface thereof by a chemical mechanical polishing method.  
     
     
         10 . The method according to    claim 6   , wherein said feeding interconnection and said third interconnection are formed in the same step.  
     
     
         11 . The method according to    claim 6   , wherein said first interconnection includes a bit line.  
     
     
         12 . A semiconductor integrated circuit device, comprising: 
 MISFETs formed over a main surface of a semiconductor substrate;    a capacitive element formed over said each MISFET; a first interconnection formed over said capacitive element;    a first insulating film formed over said first interconnection; and    a second interconnection formed over said first insulating film,    wherein said capacitive element comprises a capacitive lower electrode electrically connected to said each MISFET, a dielectric film formed over said capacitive lower electrode, and a capacitive upper electrode formed over said dielectric film and electrically connected to said second interconnection, and said first insulating film is comprised of an insulating film formed by a high-density plasma CVD method.    
     
     
         13 . The semiconductor integrated circuit device according to    claim 12   , wherein said first interconnection is electrically insulated from said each capacitive element.  
     
     
         14 . The semiconductor integrated circuit device according to    claim 12   , wherein said first interconnection is electrically connected to said capacitive element through said second interconnection.  
     
     
         15 . The semiconductor integrated circuit device according to    claim 12   , wherein said first interconnection is electrically connected to said capacitive element through said MISFET.  
     
     
         16 . The semiconductor integrated circuit device according to    claim 12   , wherein a passivation film is formed over said second interconnection.  
     
     
         17 . The semiconductor integrated circuit device according to    claim 16   , wherein said passivation film is comprised of a film obtained by laminating a silicon oxide film and a silicon nitride film formed by a CVD method on one another.  
     
     
         18 . The semiconductor integrated circuit device according to    claim 12   , wherein some of said second interconnection are bonding pads.  
     
     
         19 . The semiconductor integrated circuit device according to    claim 12   , wherein said second interconnection corresponds an uppermost wiring layer.  
     
     
         20 . A semiconductor integrated circuit device, comprising: 
 MISFETs formed over a main surface of a semiconductor substrate;    a capacitive element formed over said each MISFET; a first insulating film formed so as to surround the periphery of said capacitive element;    a first interconnection formed over said first insulating film;    a second interconnection formed over said first interconnection;    a first plug formed over said capacitive element and connecting said capacitive element and said second interconnection; and    a second plug formed over said first interconnection and connecting said first interconnection and said second interconnection.    
     
     
         21 . The semiconductor integrated circuit device according to    claim 20   , wherein the height of said first plugs is higher than that of said second plug.  
     
     
         22 . The semiconductor integrated circuit device according to    claim 20   , wherein the thickness of said first insulating film is the same degree as the height of said capacitive element.  
     
     
         23 . The semiconductor integrated circuit device according to    claim 20   , further including: 
 a third interconnection formed below said first insulating film; and    a third plug formed over said third interconnection and connecting said third interconnection and said first interconnection.    
     
     
         24 . The semiconductor integrated circuit device according to    claim 20   , wherein said capacitive element is electrically insulated from said first interconnection.  
     
     
         25 . The semiconductor integrated circuit device according to    claim 20   , wherein said capacitive element is electrically connected to said first interconnection through said second interconnection.  
     
     
         26 . The semiconductor integrated circuit device according to    claim 20   , wherein said capacitive element is electrically connected to said first interconnection through said MISFET.  
     
     
         27 . The semiconductor integrated circuit device according to    claim 20   , wherein said fist plug is separated from said first interconnection by an insulating film.  
     
     
         28 . A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 
 forming MISFETs over a main surface of a semiconductor substrate;    forming a capacitive element electrically connected to said each MISFET over said each MISFET;    forming a first insulating film for surrounding a peripheral portion of said capacitive element;    forming a first interconnection over said first insulating film;    forming a second insulating film over said first interconnection;    defining a first opening for exposing a capacitive element at the bottom of an insulating film including said second insulating film;    defining a second opening for exposing said first interconnection at the bottom of the insulating film including said second insulating film;    forming a first plug within said first opening; and    forming a second plug within said second opening.    
     
     
         29 . The method according to    claim 28   , wherein said step of defining said first opening and said step of defining said second opening are simultaneously performed.  
     
     
         30 . The method according to    claim 28   , wherein the depth of said first opening is greater than that of said second opening.  
     
     
         31 . The method according to    claim 28   , further including a step of forming a first interconnection below said first insulating film, a step of defining a third opening for exposing said first interconnection in said first insulating film; and a step of forming a third plug within said third opening.  
     
     
         32 . The method according to    claim 28   , wherein the thickness of said first insulating film is substantially the same degree as the height of said capacitive element.