High density memory structure

Abstract

A dynamic random access memory (DRAM) integrated circuit ( 10 ). The DRAM ( 10 ) includes a recessed region ( 20 ) defined in a semiconductor substrate ( 22 ). This recessed region has substantially vertical sides ( 34 ) extending from a bottom surface ( 32 ). A field effect transistor ( 18 ) is defined adjacent to the recessed region ( 20 ). A capacitor structure, including a lower capacitor plate ( 26 ), a capacitor dielectric ( 28 ), and an upper capacitor plate ( 30 ), is defined in the recessed region ( 20 ) and over the field effect transistor ( 18 ), thereby providing a greater capacitor surface.

What is claimed is:  
     
         1 . A memory device, said device comprising: 
 a semiconductor substrate comprising a recessed region, said recessed region having sides extending from a bottom surface;    a field effect transistor, said field effect transistor including a source/drain region adjacent to said recessed region;    an insulating layer overlying the recessed region;    a lower capacitor plate overlying said insulating layer and over a portion of said field effect transistor, said lower capacitor plate being connected to said source drain region;    a capacitor dielectric overlying said lower capacitor plate; and    an upper capacitor plate overlying said dielectric layer.    
     
     
         2 . Device of    claim 1    wherein said recessed region is provided with a depth ranging from about 8,000 to about 12,000 Å.  
     
     
         3 . Device of    claim 1    wherein said lower capacitor plate is provided with a thickness ranging from about 1,000 to about 1,400 Å.  
     
     
         4 . Device of    claim 1    wherein said lower capacitor plate is provided with a thickness of less than about 1,200 Å.  
     
     
         5 . Device of    claim 1    wherein said lower capacitor plate is an in-situ doped polysilicon layer.  
     
     
         6 . Device of    claim 1    wherein said upper capacitor plate is an in-situ doped polysilicon layer.  
     
     
         7 . Device of    claim 1    wherein said capacitor dielectric comprises an oxide layer.  
     
     
         8 . Device of    claim 1    wherein said capacitor dielectric comprises an oxide layer and a nitride layer.  
     
     
         9 . Device of    claim 1    wherein said field effect transistor is an MOS transistor.  
     
     
         10 . A method of forming a capacitor structure for a memory device, said method comprising: 
 providing a semiconductor substrate;    forming a recessed region, said recessed region having sides extending from a bottom surface;    forming an insulating layer defined overlying said recessed region;    forming a source/drain region adjacent to said recessed region;    forming a lower capacitor plate overlying said insulating layer and over a portion of said field effect transistor, said lower capacitor plate being connected to said source/drain region;    forming a capacitor dielectric overlying said lower capacitor plate; and    forming an upper capacitor plate overlying said dielectric layer.    
     
     
         11 . The method of    claim 10    wherein said recessed region is provided with a depth ranging from about 8,000 to about 12,000 Å.  
     
     
         12 . The method of    claim 10    wherein said lower capacitor plate is provided with a thickness ranging from about 1,000 to about 1,400 Å.  
     
     
         13 . The method of    claim 10    wherein said lower capacitor plate is provided with a thickness of less than about 1,200 Å.  
     
     
         14 . The method of    claim 10    wherein said lower capacitor plate is an in-situ doped polysilicon layer.  
     
     
         15 . The method of    claim 10    wherein said upper capacitor plate is an in-situ doped polysilicon layer.  
     
     
         16 . The method of    claim 10    wherein said capacitor dielectric comprises an oxide layer.  
     
     
         17 . The method of    claim 10    wherein said capacitor dielectric comprises an oxide layer and a nitride layer.  
     
     
         18 . The method of    claim 10    wherein said field effect transistor is an MOS transistor.  
     
     
         19 . A dynamic random access memory integrated circuit, said integrated circuit element comprising: 
 a semiconductor substrate comprising a recessed region, said recessed region having sides extending from a bottom surface;    a field effect transistor, said field effect transistor including a source/drain region adjacent to said recessed region; and    an insulating layer defined overlying said recessed region;    a conductor defined within said recessed region, said conductor being connected to said source drain region.    
     
     
         20 . A method of forming bit-line in a dynamic random access memory integrated circuit element, said method comprising: 
 providing a semiconductor substrate;    forming a recessed region in said semiconductor substrate, said recessed region having sides extending from a bottom surface;    forming an insulating layer defined overlying said recessed region;    forming a field effect transistor, said field effect transistor including a source/drain region adjacent to said recessed region; and    forming a conductor defined within said recessed region, said conductor being connected to said source drain region.