Method of fabricating a semiconductor device

Abstract

A capacitor for a semiconductor device including a lower electrode having a silicon layer with portions initially doped at different doping densities, a plurality of protrusions formed selectively on the lower electrode according to the different doping densities, a dielectric layer over the lower electrode and the protrusions, and an upper electrode over the dielectric layer. After the protrusions are formed, a step of additionally doping the lower electrode to increase the doping density thereof is not required. The silicon layer with portions initially doped at different doping densities allows the protrusions to form more easily, so that the entire surface area of the lower electrode is increased to thus minimize variations in capacitance.

What is claimed is:  
     
         1 . A method of fabricating a semiconductor device comprising: 
 forming on a substrate a first amorphous silicon layer doped with impurity ions at a first impurity density;    forming on the first amorphous silicon layer a second amorphous silicon layer doped with impurity ions at a second impurity density higher than the first impurity density;    forming on the second amorphous silicon layer a third amorphous silicon layer doped with impurity ions at a third impurity density lower than the first impurity density;    forming a predetermined pattern by patterning the first to third amorphous silicon layers;    forming hemispherical silicon grains on an exposed surface of the predetermined pattern; and    diffusing the impurity ions among the hemispherical silicon grains and the predetermined pattern so that a density of the impurity ions is uniform in the hemispherical silicon grains and the predetermined pattern.    
     
     
         2 . The method according to    claim 1   , wherein the first to third amorphous silicon layers and the hemispherical silicon grains are doped with negative impurity ions.  
     
     
         3 . The method according to    claim 1   , wherein the impurity ions are phosphorus ions.  
     
     
         4 . The method according to    claim 3   , wherein the first impurity density of the phosphorus ions lies between 1.0E20 and 1.0E21 atoms/cm 3 , the second impurity density of the phosphorus ions is over 1.0E21 atoms/cm 3 , and the third impurity density of the phosphorus ions lies between 0.0 and 1.0E20 atoms/cm 3 .  
     
     
         5 . The method according to    claim 1   , wherein the step of diffusing the impurity ions further comprises: 
 depositing a silicon nitride layer on surfaces of the hemispherical silicon grains and the predetermined pattern at a first temperature; and    oxidizing the silicon nitride layer at a second temperature.    
     
     
         6 . The method according to    claim 1   , wherein the step of diffusing the impurity ions is achieved by carrying out annealing on the hemispherical silicon grains and the predetermined pattern.  
     
     
         7 . The method according to    claim 5   , wherein after the step of oxidizing the silicon nitride layer, the method further comprises: 
 forming a conductive layer on the silicon nitride layer wherein the predetermined pattern and the hemispherical silicon grains, the silicon nitride layer, and the conductive layer respectively become a lower electrode, a dielectric layer, and an upper electrode of a capacitor.    
     
     
         8 . The method according to    claim 7   , wherein the conductive layer is formed of doped polysilicon.  
     
     
         9 . The method according to    claim 1   , wherein the hemispherical silicon grains are formed by flowing SiH 4  gases on the exposed surface of the predetermined pattern.  
     
     
         10 . The method according to    claim 1   , wherein the first to third amorphous silicon layers are formed of in-situ doped amorphous silicon at the first to third impurity densities, respectively.  
     
     
         11 . The method according to    claim 1   , wherein the first to third amorphous silicon layers are formed by depositing undoped amorphous silicon and then by doping the undoped amorphous silicon at the first to third impurity densities, respectively.  
     
     
         12 . A method of fabricating a semiconductor device comprising: 
 forming an insulating layer on a semiconductor substrate having a contact hole exposing a portion of the substrate;    forming on the insulating layer a first conductive layer contacting a predetermined portion of the semiconductor substrate;    forming on the first conductive layer a first amorphous silicon layer doped with impurity ions at a first impurity density;    forming on the first amorphous silicon layer a second amorphous silicon layer doped with the impurity ions at a second impurity density higher than the first impurity density;    forming on the second amorphous silicon layer a third amorphous silicon layer doped with the impurity ions at a third impurity density lower than the first impurity density;    forming a lower electrode by patterning the first to third amorphous silicon layers and the first conductive layer, wherein the lower electrode comprises the the first to third amorphous silicon layers and the first conductive layer;    forming hemispherical silicon grains on an exposed surface of the lower electrode;    forming a dielectric layer on exposed surfaces of the lower electrode and the hemispherical silicon grains; and    forming on the dielectric layer an upper electrode using a second conductive layer.    
     
     
         13 . The method according to    claim 12   , wherein the first to third amorphous silicon layers and the hemispherical silicon grains are doped with negative impurity ions.  
     
     
         14 . The method according to    claim 12   , wherein the impurity ions are phosphorus ions.  
     
     
         15 . The method according to    claim 14   , wherein the first impurity density of the phosphorus ions lies between 1.0E20 and 1.0E21 atoms/cm 3  the second impurity density of the phosphorus ions is over 1.0E21 atoms/cm 3 , and the third impurity density of the phosphorus ions lies between 0.0 and 1.0E20 atoms/cm 3 .  
     
     
         16 . The method according to    claim 12   , wherein the step of forming a dielectric layer further comprises: 
 depositing a silicon nitride layer on surfaces of the hemispherical silicon grains and the lower electrode at a first temperature; and    oxidizing the silicon nitride layer at a second temperature at which the impurity ions diffuse naturally.    
     
     
         17 . The method according to    claim 12   , further comprising the step of carrying out annealing on the hemispherical silicon grains and the lower electrode to diffuse the impurity ions therebetween.  
     
     
         18 . The method according to    claim 12   , wherein the second conductive layer is formed of doped polysilicon.  
     
     
         19 . The method according to    claim 12   , wherein the hemispherical silicon grains are formed by flowing SiH 4  gases on the exposed surface of the lower electrode.  
     
     
         20 . The method according to    claim 12   , wherein the first to third amorphous silicon layers are formed of in-situ doped amorphous silicon at the first to third impurity densities, respectively.  
     
     
         21 . The method according to    claim 12   , wherein the first to third amorphous silicon layers are formed by depositing undoped amorphous silicon and then by doping the undoped amorphous silicon at the first to third impurity densities, respectively.  
     
     
         22 . A method of fabricating a semiconductor device comprising: 
 forming an insulating layer on a semiconductor substrate having a contact hole exposing a portion of the substrate;    forming on the insulating layer a first conductive layer contacting a predetermined portion of the semiconductor substrate;    patterning the first conductive layer so that the first conductive layer remains in the contact hole and extends on a top surface portion of the insulating layer;    forming a pillar at a side of the remaining first conductive layers wherein the pillar is constructed using a first amorphous silicon layer doped with impurity ions at a first impurity density, a second amorphous silicon layer doped with impurity ions at a second impurity density higher than the first impurity density, and a third amorphous silicon layer doped with impurity ions at a third impurity density lower than the first impurity density, and wherein the first to third amorphous silicon layers are stacked successively;    forming hemispherical silicon grains on exposed surfaces of the remaining first conductive layer and the pillar;    forming a dielectric layer on exposed surfaces of the pillar and the hemispherical silicon grains; and    forming on the dielectric layer an upper electrode using a second conductive layer.    
     
     
         23 . The method according to    claim 22   , the step of forming the pillar further comprises: 
 forming a sacrificing layer on the first conductive layer using a substance having an etch rate that differs from that of the insulating layer;    patterning the sacrificing layer and the first conductive layer to remain in the contact hole and extends on a top surface portion of the insulating layer;    forming a first amorphous silicon layer doped with impurity ions at a first impurity density on the insulating layer including the remaining sacrificing layer and a first conductive layer pattern of the remaining first conductive layer;    forming on the first amorphous silicon layer a second amorphous silicon layer doped with impurity ions at a second impurity density higher than the first impurity density;    forming on the second amorphous silicon layer a third amorphous silicon layer doped with impurity ions at a third impurity density lower than the first impurity density;    patterning the first to third amorphous silicon layers to remain at sides of the remaining sacrificing layer and the first conductive layer pattern; and    removing the remaining sacrificing layer.    
     
     
         24 . The method according to    claim 22   , wherein a lower electrode being a storage electrode of a capacitor is constructed with the remaining first conductive layer, the pillar, and the hemispherical silicon grains.  
     
     
         25 . The method according to    claim 22   , wherein the first to third amorphous silicon layers and the hemispherical silicon grains are doped with negative impurity ions enabling to provide electric conductivity thereto.  
     
     
         26 . The method according to    claim 22   , wherein the impurity ions are phosphorus ions.  
     
     
         27 . The method according to    claim 26   , wherein the first impurity density of the phosphorus ions lies between 1.0E20 and 1.0E21 atoms/cm 3 , the second impurity density of the phosphorus ions is over 1.0E21 atoms/cm 3 , and the third impurity density of the phosphorus ions lies between 0.0 and 1.0E20 atoms/cm 3 .  
     
     
         28 . The method according to    claim 22   , the step of forming a dielectric layer further comprises: 
 depositing a silicon nitride layer on surfaces of the hemispherical silicon grains and the pillar at a first temperature; and    oxidizing the silicon nitride layer at a second temperature at which the impurity ions diffuse naturally.    
     
     
         29 . The method according to    claim 22   , the method further comprising the step of carrying out annealing on the hemispherical silicon grains and the pillar to diffuse the impurity ions therebetween.  
     
     
         30 . The method according to    claim 22   , wherein the second conductive layer is formed of doped polysilicon.  
     
     
         31 . The method according to    claim 22   , wherein the hemispherical silicon grains are formed by flowing SiH 4  gases on the exposed surfaces of the first conductive layer and the pillar.  
     
     
         32 . The method according to    claim 22   , wherein the first to third amorphous silicon layers are formed of in-situ doped amorphous silicon at the first to third impurity densities, respectively.  
     
     
         33 . The method according to    claim 22   , wherein the first to third amorphous silicon layers are formed by depositing undoped amorphous silicon and then by doping the undoped amorphous silicon at the first to third impurity densities, respectively.  
     
     
         34 . A method of forming a capacitor for a semiconductor device comprising: 
 forming a lower electrode having a silicon layer with portions initially doped at different doping densities;    forming a plurality of protrusions selectively on the lower electrode according to the different doping densities;    forming a dielectric layer over the lower electrode and the protrusions; and    forming an upper electrode over the dielectric layer.    
     
     
         35 . The method of    claim 34   , wherein the silicon layer is formed to have at least two different portions, each initially having a different doping density.  
     
     
         36 . The method of    claim 34   , wherein forming the lower electrode having the silicon layer further comprises: 
 forming a first layer at a first doping density;    forming a second layer on the first layer at a second doping density; and    forming a third layer on the second layer at a third doping density.    
     
     
         37 . The method of    claim 36   , wherein the second doping density is greater than the first doping density.  
     
     
         38 . The method of    claim 36   , wherein the second doping density is greater than the third doping density.  
     
     
         39 . The method of    claim 36   , wherein the third doping density is less than the first doping density.  
     
     
         40 . The method of    claim 36   , wherein the third doping density is the same as the first doping density.  
     
     
         41 . The method of    claim 34   , wherein the protrusions are formed by growing silicon particles on the lower electrode.  
     
     
         42 . The method of    claim 41   , wherein the protrusions are formed on the lower electrode at portions having relatively low doping densities.  
     
     
         43 . The method of    claim 34   , wherein the forming of the dielectric layer diffuses impurity ions in the silicon layer.  
     
     
         44 . The method of clam  34 , wherein a step of additionally doping the lower electrode after the protrusions are formed is not required.  
     
     
         45 . A capacitor for a semiconductor device formed by a process comprising: 
 forming a lower electrode having a silicon layer with portions initially doped at different doping densities;    forming a plurality of protrusions selectively on the lower electrode according to the different doping densities;    forming a dielectric layer over the lower electrode and the protrusions; and    forming an upper electrode over the dielectric layer.    
     
     
         46 . The capacitor of    claim 45   , wherein the silicon layer has at least two portions, each initially having a different doping density.