Process for manufacturing semiconductor device and exposure mask

Abstract

In a process for manufacturing a semiconductor device where a plurality of wafers are formed on a single wafer, comprising the steps of forming a groove pattern in an insulating layer on a wafer; forming a seed metal layer in the groove by spattering; depositing an interconnection metal layer on the seed metal layer by electrolytic plating; and then flattering the wafer to the surface of the insulating layer, during forming the groove pattern in the insulating layer, the groove pattern is formed in the area on the wafer where devices can be taken while forming a dummy pattern up to 30 μm long in the wafer periphery where devices cannot be taken, to prevent the interconnection metal layer from being peeled in the wafer periphery.

What is claimed is:  
     
         1 . A process for manufacturing a semiconductor device where a plurality of wafers are formed on a single wafer, comprising the steps of forming a groove pattern in an insulating layer on a wafer; forming a seed metal layer in the groove by spattering; depositing an interconnection metal layer on the seed metal layer by electrolytic plating; and then flattering the wafer to the surface of the insulating layer, wherein during forming the groove pattern in the insulating layer, the groove pattern is formed in the area on the wafer where devices can be taken while forming a dummy pattern up to 30 μm long in the wafer periphery where devices cannot be taken.  
     
     
         2 . A process for manufacturing a semiconductor device as claimed in    claim 1    where the data ratio of the mask for forming the dummy pattern in the wafer periphery where devices cannot be taken is 10% or higher.  
     
     
         3 . A process for manufacturing a semiconductor device as claimed in    claim 1    where the groove pattern and the dummy pattern are formed by photolithography and dummy pattern exposure is conducted before groove pattern exposure for the device area.  
     
     
         4 . A process for manufacturing a semiconductor device as claimed in    claim 1    where the interconnection metal layer consists of copper or a copper alloy.  
     
     
         5 . A process for manufacturing a semiconductor device as claimed in    claim 4    where the seed metal layer is a spattered copper film.  
     
     
         6 . A process for manufacturing a semiconductor device as claimed in    claim 1    where there is a barrier metal layer between the seed metal layer and the insulating layer.