US2001026383A1PendingUtilityA1

Fiber optic interface and system

Assignee: AMERICAN AUTO MATRIX INCPriority: Jun 8, 1990Filed: Apr 30, 2001Published: Oct 4, 2001
Est. expiryJun 8, 2010(expired)· nominal 20-yr term from priority
Inventors:Warren Cecchini
H04B 10/2589
36
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An apparatus for optically connecting at least two independent half-duplex networks. The apparatus receives electrical signals from a first network, converts these signals to optical signals, and then transmits the optical signals along optical fiber to another apparatus. This apparatus converts the optical signals it receives to electrical signals and transmits the signals to the second network. The apparatus controls the flow signals to and from the networks and optical fibers without any external control signals.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An apparatus comprising: 
 a first fiber receiver for receiving optical digital signals from a first optical fiber;    a second fiber receiver for receiving optical digital signals from a second optical fiber;    an interface which connects to the first and second fiber receivers and to a half duplex line for receiving electrical digital signals from the half duplex line and sending electrical digital signals thereto corresponding to optical digital signals received from either the first or second fiber receivers;    a first fiber transmitter means for providing optical digital signals to a third optical fiber corresponding to digital signals received from the first or second fiber receivers or the interface;    a second fiber transmitter means for providing optical digital signals to a fourth optical fiber corresponding to signals received from the first or second fiber receivers or the interface;    a fiber receive data merger connected to the first and second fiber receivers for merging the signals therefrom and producing a corresponding signal;    a first trigger circuit connected to the interface and the first and second fiber transmitters and the interface for passing signals from the interface to the transmitters and the interface when the first trigger circuit is in a first state;    a second trigger circuit connected to the fiber receive data merger and to the interface, and the first and second fiber transmitter, for passing signals from the fiber receive data merger to the interface and to the first and second fiber transmitters when the second trigger circuit is in a first state; and    means for controlling when the first and second trigger circuits are in the first state, said controlling means preventing the first and second trigger circuit from being in the first state at the same time and for preventing one of the trigger circuits from being in the first state for at least a predetermined period of time corresponding to a number of bits after the other trigger circuit is in the first state.    
     
     
         2 . An apparatus as described in    claim 1    wherein the controlling means includes a first trigger interlock connected to the first and second trigger circuits for locking out the second trigger circuit from the first state while the first trigger circuit is in the first state and for the predetermined period of time thereafter; 
 a first bit timer connected to the first trigger interlock for providing a signal to the first trigger interlock causing the first trigger interlock to unlock the second trigger circuit when the predetermined period of time has passed;  
 a second trigger interlock connected to the first and second trigger circuits for locking out the first trigger circuit from the first state while the second trigger circuit is in the first state and for the predetermined period of time thereafter; and  
 a second bit timer connected to the second trigger interlock for providing a signal to the second trigger interlock causing the second trigger interlock to unlock the first trigger circuit when the predetermined period of time has passed.  
 
     
     
         3 . An apparatus as described in    claim 2    wherein the predetermined period of time corresponds to essentially one bit.

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