Semiconductor device and the method for manufacturing the same

Abstract

A semiconductor device includes, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed, and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the first chip top surface is fixed on the die pad bottom surface, the second chip bottom surface is fixed on the die pad top surface.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a die pad having a die pad top surface and a die pad bottom surface;    a first semiconductor chip having a first chip top surface and a first chip bottom surface, and the first chip top surface having a first plurality of electrodes thereon,    a second semiconductor chip having a second chip top surface and a second chip bottom surface, the second chip top surface having a second plurality of electrodes thereon, and the second semiconductor chip being smaller than the first semiconductor chip;    wherein the first chip top surface is fixed under the die pad bottom surface, the second chip bottom surface is fixed over the die pad top surface.    
     
     
         2 . The semiconductor device according to    claim 1   , wherein the second semiconductor chip is smaller than the die pad.  
     
     
         3 . The semiconductor device according to    claim 1   , wherein the area of the die pad bottom surface is smaller than half of the area of the first chip top surface.  
     
     
         4 . The semiconductor device according to    claim 1   , wherein the first semiconductor chip is a logic semiconductor chip, and the second semiconductor chip is a memory semiconductor chip.  
     
     
         5 . The semiconductor device according to    claim 1   , further comprising inner leads, wherein the inner leads and the die pad are formed substantially at the same level.  
     
     
         6 . The semiconductor device according to    claim 1   , wherein the first plurality of electrodes are disposed on the outside of a region that is defined by an edge of the second semiconductor chip.  
     
     
         7 . The semiconductor device according to    claim 1   , wherein the first plurality of electrodes are disposed on the outside of the die pad.  
     
     
         8 . The semiconductor device according to    claim 6   , further comprising a metal wire which electrically connects at least one of the first plurality of electrodes to at least one of the second plurality of electrodes.  
     
     
         9 . The semiconductor device according to    claim 3   , further comprising 
 a first metal wire which connects at least one of the first plurality of electrodes to the inner leads;    a second metal wire which connects at least one of the second plurality of electrodes to the inner leads.    
     
     
         10 . The semiconductor device according to    claim 8   , wherein the first metal wire and the second metal wire are formed in a side of the die pad top surface.  
     
     
         11 . The semiconductor device according to    claim 1   , further comprising: 
 a molding resin that molds the first semiconductor chip, the second semiconductor chip, and the die pad,    wherein the thickness of the resin over the second semiconductor chip is substantially the same as the thickness of the resin under the first semiconductor chip.    
     
     
         12 . A method for manufacturing the semiconductor device comprising 
 forming a first adhesive layer over a die pad bottom surface;    forming a second adhesive layer over a die pad top surface;    fixing a top surface of a first semiconductor chip on the first adhesive layer, the top surface of the first semiconductor chip having a first plurality of electrodes thereon, and    fixing a bottom surface of a second semiconductor chip, which is smaller than the first semiconductor chip, on the second adhesive layer, a top surface of the second semiconductor chip having a second plurality of electrodes thereon.    
     
     
         13 . The method according to    claim 12   , wherein forming the second adhesive layer is performed after fixing the first semiconductor layer.  
     
     
         14 . The method according to    claim 12   , wherein the first adhesive layer and the second adhesive layer have a thermosetting characteristic.  
     
     
         15 . The method according to    claim 14   , wherein a second hardening temperature of the second adhesive layer is higher than a first hardening temperature of the first adhesive layer.  
     
     
         16 . The method according to claim.  12 , wherein the first adhesive layer and the second adhesive layer have a thermoplastic characteristic.  
     
     
         17 . The method according to    claim 16   , wherein a second softening temperature of the second adhesive layer is lower than a first softening temperature of the first adhesive layer.  
     
     
         18 . The method according to    claim 14   , wherein the first adhesive layer and the second adhesive layer are partly formed on the die pad top surface and the die pad bottom surface, a first portion on the die pad bottom surface, which corresponds to the first adhesive layer is different from a second portion on the die pad top surface which corresponds to the second adhesive layer.  
     
     
         19 . The method according to    claim 16   , wherein the first adhesive layer and the second adhesive layer are partly formed on the die pad top surface and the die pad bottom surface, a first portion on the die pad bottom surface, which corresponds to the first adhesive layer is different from a second portion on the die pad top surface which corresponds to the second adhesive layer.  
     
     
         20 . The method according to    claim 12   , further comprising; 
 connecting some of the first plurality of electrodes on the first semiconductor chip to some of the second plurality of electrodes on the second semiconductor chip,    wherein the electrodes on the first semiconductor chip are disposed on the outside of the region that is defined by an edge of the second semiconductor chip.    
     
     
         21 . The method according to    claim 12   , further comprising; 
 first connecting at least one of the first plurality of electrodes on the first semiconductor chip to at least one of inner leads;    second connecting at least one of the second plurality of electrodes on the second semiconductor chip to at least one of inner leads,    wherein said first connecting and second connecting is performed subsequently in the same step.