Method of increasing package reliability using package lids with plane CTE Gradients

Abstract

A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.

What is claimed is:  
     
         1 . A method of improving reliability for a chip/package system, comprising the steps of: 
 forming a package that exhibits first and second discrete coefficients of thermal expansion (CTEs) in first and second discrete regions thereof.    
     
     
         2 . A method according to    claim 1   , wherein the first region is a defined by a chip mounting area.  
     
     
         3 . A method according to    claim 1   , wherein package is a laminated substrate having first and second outer, opposite surfaces.  
     
     
         4 . A method according to    claim 3   , wherein the first outer surface has a central chip mounting area, and the first region is defined by the chip mounting area and the second region is defined by the area of the first outer surface that surrounds the chip mounting area.  
     
     
         5 . A method according to    claim 4   , wherein the second outer surface is connectable to a printed wiring board (PWB).  
     
     
         6 . A method according to    claim 1   , wherein the first region is made of materials selected to achieve a CTE that approximates the CTE of the integrated circuit chip.  
     
     
         7 . A method according to    claim 6   , wherein the second region is made of materials selected to achieve a CTE that approximates the CTE of the PWB.  
     
     
         8 . A method according to    claim 1   , wherein the CTE of the first region is lower than the CTE of the second region.  
     
     
         9 . A method according to    claim 1   , wherein the package has first and second opposite surfaces, the chip is connectable to the first surface and the first region is defined by an area under the chip.  
     
     
         10 . A method according to    claim 1   , wherein the package is a laminated substrate having a plurality of alternatingly disposed dielectric and conductive layers.  
     
     
         11 . A method according to    claim 10   , wherein the dielectric layers are made substantially of an organic material.  
     
     
         12 . A method according to    claim 11   , wherein the organic material is an expanded polytetrafluoroethylene (ePTFE) impregnated with cyanate ester epoxy.