Analog to digital switched capacitor converter using a delta sigma modulator having very low power, distortion and noise

Abstract

Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

What is claimed is:  
     
         1 . An analog to digital converter, comprising: 
 a. an analog input;    b. a combination circuit connected to said analog input;    c. an integrator receiving the output of the combination circuit, and having a plurality of stages with at least one stage having different power levels available during respective operational phases;    d. a summing circuit receiving a weighted outputs from at least two of said stages and producing a summed output; and    e. a comparator receiving said summed output and, when said summed output exceeds a certain threshold value, providing a digital output signal to an output and to said combination circuit.    
     
     
         2 . The analog to digital converter of    claim 1    in which said integrator comprises a plurality of series connected stages with at least one stage having said combination circuit as an input circuit and said combination circuit comprises: 
 a switched capacitor input circuit; and  
 a feedback input.  
 
     
     
         3 . The analog to digital circuit of    claim 2    in which at least one stage of said integrator comprises an amplifier circuit having a capacitor connected between an output and one input of said amplifier circuit.  
     
     
         4 . The analog to digital circuit of    claim 3    in which said switched capacitor input circuit and said feedback input are connected to said capacitor and said one input.  
     
     
         5 . The analog to digital circuit of    claim 3    in which said amplifier circuit comprises a power control circuit configured to provide high power to an active element during at least one portion of an amplifier's operational cycle and to provide low power otherwise.  
     
     
         6 . The analog to digital circuit of    claim 5    in which said power control circuit comprises two current mirrors in parallel.  
     
     
         7 . The analog to digital circuit of    claim 6    in which one of said current mirrors is larger in capacity than the other.  
     
     
         8 . The analog to digital circuit of    claim 5    in which one of said current mirrors is selectively activated only during said portion of an operational cycle.  
     
     
         9 . The analog to digital circuit of    claim 8    in which said portion of an operational cycle comprises at least part of a slewing phase.  
     
     
         10 . The analog to digital circuit of    claim 5    in which said amplifier circuit comprises an amplifier having an input receiving a digital signal; an active element receiving said signal from said input; and a power control circuit having two output levels connected to said active element and selectively providing one of said levels to said element only during a portion of its operating time.  
     
     
         11 . The analog to digital circuit of    claim 5    in which said amplifier circuit comprises two current sources and an active element, connected to said current sources so that only one current source is active during an operational phase when power requirements are relatively low and so that both current sources are active during an operational phase when power requirements are relatively high.  
     
     
         12 . The analog to digital circuit of    claim 5    in which said amplifier circuit includes a control circuit comprising: 
 a. a first current source connected in series with a first active device and a second active device, with each active device having a gate terminal;  
 b. a second constant current source connected in series with a third active device and a fourth active device, each active device having a gate terminal, with the gates of said third active device and said second active device connected together; and  
 c. an output device having a gate terminal connected to the junction of said second current source and said third active device and controlled thereby.  
 
     
     
         13 . The analog to digital circuit of    claim 1    in which the step size of the digital output applied to said combination circuit is optimized to conserve power.  
     
     
         14 . An analog to digital converter comprising: 
 a. an analog signal input;    b. a delta modulator receiving said analog signal input, said delta modulator sampling said analog signal input at a rate substantially in excess of the Nyquist rate, and    c. a multistage integrator, in which weighted values of outputs of stages of said multistage integrator are combined to form a feedback signal,    in which said feedback signal is combined with a signal from said analog signal input,    in which power is provided to said delta modulator in a high power during slewing and in a low power mode at other times.    
     
     
         15 . A method of operating an analog to digital converter, comprising the steps of: 
 a. oversampling the analog input signal to produce an oversampled digital output signal,    b. applying the oversampled digital output signal to a multistage integrator,    c. weighing a signal output from each stage of said multistage integrator to form a feedback signal and combining the feedback signal with the analog input signal and controlling power to at least one stage of said multistage integrator to increase power during less than all of its operation cycle.    
     
     
         16 . A method of providing power to a clocked analog to digital converter comprising the step of: 
 providing different power levels to said analog to digital converter during at least two respective time intervals separated by one or more clock signals.    
     
     
         17 . A method of controlling current to an analog to digital converter, comprising the step of: 
 during an operational phase when slew is expected, increasing current available to the analog to digital converter irrespective of actual signal level applied to the analog to digital converter.    
     
     
         18 . A method of controlling current to an integrator, comprising the step of: 
 decreasing current available to the analog to digital converter during an operational phase when little activity is expected.    
     
     
         19 . A method of providing power to an analog to digital converter comprising the steps of: 
 using two current mirrors to provide power to at least one element of the analog to digital converter; and    switching one current mirror in or out to control power to the analog to digital converter without adversely affecting the integrator.    
     
     
         20 . A method for saving power in a delta sigma modulator, comprising the step of: 
 running at a greater oversampling rate than required by signal to quantization noise requirements.    
     
     
         21 . A method for saving power in a delta sigma modulator, comprising the step of: 
 optimizing feedback coefficients from an integrating circuit for reduced power consumption.    
     
     
         22 . A method for saving power in a delta sigma modulator, comprising the step of: 
 controlling power to a switched capacitor circuit commensurate with activity expected during an operational phase.    
     
     
         23 . A method for saving power in a delta sigma modulator, comprising the step of: 
 maximizing the step size of the delta sigma modulator for power consumption savings.    
     
     
         24 . An integrated circuit, comprising a delta sigma modulator having one or more of: 
 a. at least one stage having different power levels available during respective operational phases;    b. a greater oversampling rate than required by signal to quantization noise requirements;    c. feedback coefficients from an integrating circuit optimized for reduced power consumption; and    d. step size maximized for power consumption savings.