Interconnect structure of semiconductor device and method for manufacturing same

Abstract

An interconnect structure of a semiconductor device includes: a bottom interconnect layer formed in a dielectric layer overlying a silicon substrate; a top interconnect layer having aluminum as a main component and connected with the bottom interconnect layer by way of a via plug formed in the dielectric layer; and a first barrier metal layer having higher <111> orientation. The higher <111> orientation degree of the first barrier metal layer aluminum suppresses occurrence and growth of electro-migration provide a reliable interconnect structure.

What is claimed is:  
     
         1 . An interconnect structure of a semiconductor device comprising: 
 a silicon substrate;    a bottom interconnect layer formed in a dielectric layer overlying the silicon substrate;    a top interconnect layer having aluminum as a main component and connected with the bottom interconnect layer by way of a via plug formed in the dielectric layer; and    a <111> oriented first barrier metal layer disposed between the via plug and the top interconnect layer.    
     
     
         2 . The interconnect structure as defined in    claim 1   , wherein the first barrier metal layer is a stacked film including a Ti layer and a TiN layer disposed thereon.  
     
     
         3 . The interconnect structure as defined in    claim 1   , wherein the via plug includes a second barrier metal layer and a tungsten layer, and the top interconnect layer is made of an Al—Cu alloy.  
     
     
         4 . The interconnect structure as defined in    claim 2   , wherein thicknesses of the Ti layer and the TiN layer of the first barrier metal layer are not less than 20 nm and not less than 25 nm, respectively.  
     
     
         5 . The interconnect structure as defined in    claim 1   , wherein a top layer of the dielectric layer is made of plasma oxide.  
     
     
         6 . A method for manufacturing an interconnect structure of a semiconductor device, comprising the steps of: 
 forming a bottom interconnect layer underlying a dielectric layer and overlying a silicon substrate;    forming a through-hole in the dielectric layer to expose the bottom interconnect layer;    depositing a first barrier metal layer overlying the dielectric layer and on an inner wall of the through-hole;    depositing a metal layer on the first barrier metal layer for filling the through-hole;    etching the metal layer and the first barrier metal layer until the dielectric film is exposed to thereby form a via plug of the metal layer and the barrier metal layer;    depositing a second barrier metal layer on the dielectric film and the via plug; and    depositing an interconnect layer of which a main component is aluminum on the second barrier metal layer.    
     
     
         7 . The method as defined in    claim 6   , wherein the second barrier metal layer is formed by sequentially depositing a Ti layer and a TiN layer by sputtering.  
     
     
         8 . The method as defined in    claim 6   , wherein CMP polishing is employed for removing the metal layer and the first barrier metal layer in the via plug forming step.  
     
     
         9 . The method as defined in    claim 7   , wherein the TiN layer is continuously deposited by sputtering after the deposition of the Ti layer.  
     
     
         10 . The method as defined in    claim 7   , wherein the interconnect layer is continuously deposited by sputtering after the deposition of the TiN layer.  
     
     
         11 . The method as defined in    claim 7    further comprising a Ti layer and a TiN layer on the interconnect layer which are deposited after the interconnect layer is cooled for a specified period of time upon the completion of the interconnect layer depositing step.  
     
     
         12 . The method as defined in    claim 6   , wherein the interconnect layer is made of an Al—Cu alloy.  
     
     
         13 . The method as defined in    claim 6   , wherein the interconnect layer is <111> oriented.