Method of fabricating triple polysilicon non-volatile memory cells

Abstract

A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.

What is claimed is:  
     
         1 . A method of fabricating an array of non-volatile memory cells in a silicon substrate, the method comprising: 
 (A) forming over the substrate a plurality of pairs of stacks of first and second layer polysilicon along a row, the first layer being insulated from the substrate, and the second layer being insulated from the first layer;    (B) forming in the substrate a drain region between the two stacks in each pair of polysilicon stacks, each drain region being self-aligned to the edges of the two stacks between which the drain region is formed;    (C) forming side-wall spacers adjacent to edges of each polysilicon stack; and    (D) forming in the substrate a source region between each of two adjacent pairs of polysilicon stacks, each source region being self-aligned to the edges of the oxide spacers.    
     
     
         2 . The method of    claim 1    wherein the array is a contact-less array.  
     
     
         3 . The method of    claim 2    further comprising: 
 (E) forming a composite layer of, in the order from bottom to top, HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediately after step (B).  
 
     
     
         4 . The method of    claim 3    further comprising: 
 (F) planarizing the surface area of the array after step (D) using an insulating material.  
 
     
     
         5 . The method of    claim 4    further comprising: 
 (G) selectively removing the insulating material from over the row of cells after step (F) thereby creating a trench directly over the row of cells.  
 
     
     
         6 . The method of    claim 5    further comprising: 
 (H) converting the ONP composite layer to ONO composite layer after step (G).  
 
     
     
         7 . The method of    claim 6    further comprising: 
 (I) anisotropically etching the ONO composite layer to form ONO side-wall spacers adjacent to edges of the polysilicon stacks after step (H).  
 
     
     
         8 . The method of    claim 7    further comprising: 
 (J) growing select gate oxide over the row of polysilicon stacks after step (I).  
 
     
     
         9 . The method of    claim 8    further comprising: 
 (K) forming a third layer of polysilicon over the row of polysilicon stacks after step (J), the third layer of polysilicon forming a wordline in the array.  
 
     
     
         10 . The method of    claim 9    further comprising: 
 (L) over laying the third layer of polysilicon with a layer of metal.  
 
     
     
         11 . The method of    claim 10    wherein the first layer of polysilicon forms the floating gate, the second layer of polysilicon forms the control gate, and the third layer of polysilicon forms the select gate.  
     
     
         12 . The method of    claim 10    wherein step (A) further comprises overlaying the second layer polysilicon with tungsten silicide.  
     
     
         13 . The method of    claim 10    wherein the side-wall spacers in step (C) are from silicon dioxide.  
     
     
         14 . The method of    claim 13    wherein the side-wall spacers in step (C) are created by anisotropically etching a layer of oxide.  
     
     
         15 . The method of    claim 14    wherein step (C) causes the space between the two stacks in each pair of polysilicon stacks to fill with oxide.  
     
     
         16 . The method of    claim 10    wherein the distance between two adjacent pairs of polysilicon stacks is greater than the distance between the two stacks in each pair of polysilicon stacks.  
     
     
         17 . The method of    claim 16    wherein the distance between two adjacent pairs of polysilicon stacks is three times the distance between the two stacks in each pair of polysilicon stacks.  
     
     
         18 . The method of    claim 10    wherein the source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is formed.  
     
     
         19 . The method of    claim 10    wherein step (B) comprises: 
 (M) covering the silicon substrate regions between adjacent pairs of polysilicon stacks with photoresist; and  
 (N) implanting Arsenic into the exposed silicon substrate regions.  
 
     
     
         20 . The method of    claim 10    wherein step (J) is carried out using a thermal oxidation process.  
     
     
         21 . The method of    claim 10    wherein the select gate oxide comprises a thin layer of ONO composite layer.  
     
     
         22 . The method of    claim 10    wherein step (H) is carried out by oxidizing the conductive polysilicon layer of the ONP composite layer.  
     
     
         23 . The method of    claim 10    wherein step (K) is carried out by uniformly etching back a third layer of polysilicon deposited over the entire array without using a photoresist mask.  
     
     
         24 . The method of    claim 10    wherein step (A) is carried out in accordance with conventional ETOX process.  
     
     
         25 . The method of    claim 10    wherein the Chemical Mechanical Polish (CMP) technique or the resist etch back process is used to planarize the array.  
     
     
         26 . The method of    claim 10    wherein the memory cells are split gate cells and every two adjacent split gate cells along the row are mirror images of one another.  
     
     
         27 . A contact-less array of non-volatile memory cells comprising: 
 a row of pairs of stacks of first and second polysilicon layers over a silicon substrate, the first layer polysilicon being insulated from the substrate, and the second layer polysilicon being insulated from the first layer polysilicon;    a drain region in the substrate between the two stacks in each pair of polysilicon stacks, the drain region being self-aligned to the edges of the two stacks;    a source region in the substrate between two adjacent pairs of polysilicon stacks, the source region being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks, such that the source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located; and    a third layer of polysilicon over but insulated from the polysilicon stacks, the third layer of polysilicon forming a wordline in the array.    
     
     
         28 . The array of    claim 27    further comprising an ONO side-wall spacer adjacent to each edge of the stacks of polysilicon for insulating the side-walls of each polysilicon stack from the third layer polysilicon.  
     
     
         29 . The array of    claim 28    wherein the distance between two adjacent pairs of polysilicon stacks is greater than the distance between the two stacks in each pair of polysilicon stacks.  
     
     
         30 . The array of    claim 29    wherein the memory cells are split gate cells and every two adjacent split gate cells along the row are mirror images of one another.  
     
     
         31 . The array of    claim 29    wherein the distance between two adjacent pairs of polysilicon stacks is three times the distance between the two stacks in each pair of polysilicon stacks.  
     
     
         32 . The array of    claim 29    further comprising a layer of metal overlying the third layer of polysilicon.  
     
     
         33 . The array of    claim 32    further comprising a layer of tungsten silicide overlying the second layer of polysilicon.  
     
     
         34 . The array of    claim 29    wherein the insulating layer between the second and third layer polysilicon comprises a thin layer of oxide-nitride-oxide (ONO) composite layer.  
     
     
         35 . The array of    claim 29    wherein the pairs of stacks of first and second layer of polysilicon are formed in accordance with conventional ETOX process.  
     
     
         36 . The array of    claim 29    wherein the drain region is formed by covering the silicon substrate regions between adjacent pairs of polysilicon stacks with photoresist and implanting Arsenic into the exposed silicon substrate regions.  
     
     
         37 . The array of    claim 29    wherein the source region is formed by implanting Arsenic through a window formed by oxide side-wall spacers temporarily formed adjacent to each polysilicon stack whereby the source region is self-aligned to the side-wall spacers.  
     
     
         38 . The array of    claim 37    wherein a composite layer of, in the order from bottom to top, HTO-Nitride-Polysilicon (ONP) is formed between the oxide side-wall spacers and the stacks of polysilicon prior to source region formation.  
     
     
         39 . The array of    claim 38    wherein the top polysilicon layer in the ONP composite layer is rendered non-conductive before deposition of the third layer polysilicon.  
     
     
         40 . The array of    claim 39    wherein the top polysilicon layer in the ONP composite layer is rendered non-conductive by oxidizing the polysilicon layer.  
     
     
         41 . The array of    claim 29    wherein the array of memory cells is planarized before the third layer of polysilicon is deposited.  
     
     
         42 . The array of    claim 41    wherein the wordline is formed by depositing the third layer of polysilicon in a trench formed in the planarized array over the row of polysilicon stacks.  
     
     
         43 . The array of    claim 41    wherein the Chemical Mechanical Polish (CMP) technique or the resist etch back process is used to planarize the array.  
     
     
         44 . The method of fabricating an array of non-volatile memory cells in a silicon substrate, the method comprising: 
 (A) forming over the substrate three stacks S 1 , S 2  and S 3  of first and second polysilicon layers along a row, the first layer being insulated from the substrate, and the second layer being insulated from the first layer;    (B) forming in the substrate a drain region between the stacks S 1  and S 2 , the drain region being self-aligned to the edges of the stacks S 1  and S 2 ;    (C) forming side-wall spacers adjacent to edges of each polysilicon stack; and    (D) forming in the substrate a source region between the stacks S 2  and S 3 , the source region being self-aligned to the edges of the oxide spacers.    
     
     
         45 . The method of    claim 44    wherein the array is a contact-less array.  
     
     
         46 . The method of    claim 45    further comprising: 
 (E) forming a composite layer of, in the order from bottom to top, HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediately after step (B).  
 
     
     
         47 . The method of    claim 46    further comprising: 
 (F) converting the ONP composite layer to ONO composite layer after step (D);  
 (G) anisotropically etching the ONO composite layer to form ONO side-wall spacers adjacent to edges of the polysilicon stacks; and  
 (H) growing select gate oxide over the row of polysilicon stacks.  
 
     
     
         48 . The method of    claim 47    further comprising: 
 (I) forming a third layer of polysilicon over the row of polysilicon stacks after step (H), the third layer of polysilicon forming a wordline in the array; and  
 (J) overlying the third layer of polysilicon with a layer of metal.  
 
     
     
         49 . The method of    claim 44    wherein step (B) comprises: 
 (K) covering the silicon substrate region between stacks S 2  and S 3  with photoresist; and  
 (L) implanting Arsenic whereby drain regions are formed in the silicon substrate region between stacks S 1  and S 2 .  
 
     
     
         50 . The method of    claim 48    wherein step (A) is carried out in accordance with conventional ETOX process.  
     
     
         51 . The method of    claim 45    wherein the distance between the stacks S 2  and S 3  is greater than the distance between the stacks S 1  and S 2 .  
     
     
         52 . The method of    claim 45    wherein the distance between the S 2  and S 3  is three times the distance between the stacks S 1  and S 2 .  
     
     
         53 . A Contact-less array of non-volatile memory cells comprising: 
 three stacks S 1 , S 2  and S 3  of first and second polysilicon layers over a silicon substrate along a row, the first layer polysilicon being insulated from the substrate, and the second layer polysilicon being insulated from the first layer polysilicon;    a drain region in the substrate between the stacks S 1  and S 2 , the drain region being self-aligned to the edges of the stacks S 1  and S 2 ;    a source region in the substrate between the stacks S 2  and S 3 , the source region being self-aligned to side-wall spacers formed adjacent to edges of the stacks S 2  and S 3 , such that the source region is laterally spaced an equal distance from the edges of the stacks S 2  and S 3 ; and    a third layer of polysilicon over but insulated from the polysilicon stacks, the third layer of polysilicon forming a wordline in the array.    
     
     
         54 . The array of    claim 53    further comprising an ONO side-wall spacer adjacent to each edge of the polysilicon stacks for insulating the side-walls of each polysilicon stack from the third layer polysilicon.  
     
     
         55 . The array of    claim 53    wherein the distance between the stacks S 2  and S 3  is greater than the distance between the stacks S 1  and S 2 .  
     
     
         56 . The array of    claim 53    wherein the distance between the stacks S 2  and S 3  is three times the distance between the stacks S 1  and S 2 .  
     
     
         57 . The array of    claim 55    wherein the memory cells are split gate cells and every two adjacent split gate cells along the row are mirror images of one another.  
     
     
         58 . A method of fabricating a non-volatile memory cell in a silicon substrate, the method comprising: 
 (A) Forming over the substrate a stack of first and second polysilicon layers, the first layer being insulated from the substrate, and the second layer being insulated from the first layer; and    (B) Forming a layer of nitride adjacent the edges of the stack for protecting the edges of the stack, the nitride layer being insulated from the edges of the stack.    
     
     
         59 . The method of    claim 58    wherein step (B) further comprises: 
 (C) depositing a composite layer of, in the order from bottom to top, oxide-nitride-oxide (ONO) over the memory cell;  
 (D) anisotropically etching the top oxide layer of the ONO composite layer; and  
 (E) etching the nitride.  
 
     
     
         60 . The method of    claim 59    wherein step (B) further comprises: 
 (E) etching the bottom layer of the ONO composite layer after step (E).  
 
     
     
         61 . A non-volatile memory cell comprising: 
 a stack of first and second polysilicon layers over a silicon substrate, the first layer being insulated from the substrate, and the second layer being insulated from the first layer; and    a layer of nitride adjacent the edges of the stack for protecting the edges of the, the nitride layer being insulated from the edges of the stack.    
     
     
         62 . The memory cell of    claim 61    wherein the nitride layer forms the middle layer of a composite layer of, in the order from bottom to top, oxide-nitride-oxide (ONO).  
     
     
         63 . The memory cell of    claim 62    wherein the ONO composite layer is in the form of spacers adjacent to the edges of the stack.