Digital demodulator

Abstract

A digital demodulator which demodulates information signals that have been phase-modulated using a method such as PSK (Phase Shift Keying). The adder 46 adds a compensation value held by the phase compensator 45 to phase difference data outputted from the comparator 43. The subtractor 47 subtracts phase difference data delayed by the delaying circuit 44 by one information symbol period from the sum of the phase difference data and the compensation value from the adder 46, thus performing delay detection. With this digital demodulator, an input signal can be received and demodulated even if its frequency is not an integral division of the frequency of a master clock signal, and an oscillator can be used even if its frequency is not an integral multiple of the frequency of an input signal to be demodulated.

What is claimed is:  
     
         1 . A digital demodulator comprising: 
 phase difference data output means for comparing a phase-modulated input signal with a clock signal which is not in synchronization with the carrier wave component of the input signal, and outputting phase difference data which corresponds to the phase difference between the input signal and the clock signal;    delaying means for delaying the phase difference data outputted from said phase difference data output means by a predetermined period of time;    compensation value hold means for holding a compensation value which corresponds to a phase shift caused by the frequency difference between the carrier wave component and the clock signal;    delay detection means for detecting a delay of the phase difference data outputted from said phase difference data output means using the phase difference data outputted from said phase difference data output means, the compensation value held by said compensation value hold means, and the phase difference data delayed by said delaying means by the predetermined period of time; and    demodulation means for demodulating the input signal based on the result of the delay detection.    
     
     
         2 . A digital demodulator according to    claim 1   , wherein said delay detection means comprises: 
 addition means for adding the phase difference data outputted from said phase difference data output means and the compensation value held by said compensation value hold means; and    subtraction means for subtracting the phase difference data delayed by said delaying means by the predetermined period of time from the result of the addition by said addition means.    
     
     
         3 . A digital demodulator according to    claim 1   , wherein said delay detection means comprises: 
 subtraction means for subtracting the phase difference data delayed by said delaying means by the predetermined period of time from the phase difference data outputted from said phase difference data output means; and    addition means for adding the subtraction result of said subtraction means and the compensation value held by said compensation value hold means.    
     
     
         4 . A digital demodulator according to    claim 1   , wherein said delay detection means comprises: 
 first subtraction means for subtracting the compensation value held by said compensation value hold means from the phase difference data delayed by said delaying means by the predetermined period of time; and    second subtraction means for subtracting the subtraction result of said first subtraction means from the phase difference data outputted from said phase difference data output means.    
     
     
         5 . A digital demodulator comprises: 
 phase difference data output means for comparing an input signal with a clock signal and outputting phase difference data of the input signal;    compensation value hold means for holding a compensation value which corresponds to a phase shift caused by the frequency difference between the input signal and the clock signal;    first subtraction means for subtracting the compensation value held by said compensation value hold means from the phase difference-data outputted from said phase difference data output means;    delaying means for delaying phase difference data which is the subtraction result of said first subtraction means by a predetermined period of time;    second subtraction means for subtracting the phase difference data delayed by said delaying means by the predetermined period of time from the phase difference data outputted from said phase data output means; and    demodulation means for demodulating the input signal based on the subtraction result of said second subtraction means.    
     
     
         6 . A digital demodulator according to one of    claims 1    to    5   , wherein said addition means and said subtraction means perform addition and subtraction, respectively, in accordance with a second clock signal which is in synchronization with information symbol periods.  
     
     
         7 . A digital demodulator according to one of    claims 1    to    6   , wherein the predetermined delay period of time caused by said delaying means is the information symbol period.