Semiconductor package and manufacturing method thereof

Abstract

In order to suppress the warp of a semiconductor package of an over-coat structure, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are αr, Er and Hr, respectively, the value R of (αr·Er·Hr)/(αs·Es·Hs) is set to be approximately 0.6 or more. With adoption of such a configuration, stress exerting on a semiconductor package can be effectively alleviated, and coplanarity of the semiconductor package can be improved.

What is claimed is:  
     
         1 . A semiconductor package, comprising: 
 a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounds the first area, and at least a first connecting pad arranged in the first area;    a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type;    at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and    a resin layer disposed on the first face of the wiring substrate, the resin layer disposed so that the second face of the semiconductor element being exposed, side faces of the semiconductor element being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor element being filled.    
     
     
         2 . The semiconductor package as set forth in    claim 1   , 
 wherein the resin layer having a first face substantially in parallel with the first face of the wiring substrate, and the first face of the resin layer is substantially flushed with the second face of the semiconductor element.    
     
     
         3 . The semiconductor package as set forth in    claim 2   , 
 wherein side faces of the resin layer for sealing is inclined, and the first face of the wiring substrate is larger than the first face of the resin layer.    
     
     
         4 . The semiconductor package as set forth in    claim 1   , 
 wherein the second area of the first face of the wiring substrate is substantially covered with the resin layer.    
     
     
         5 . The semiconductor package as set forth in    claim 1   , further comprising a conductive plate disposed on the second face of the semiconductor element.  
     
     
         6 . The semiconductor package as set forth in    claim 5   , 
 wherein the conductive plate and the second face of the semiconductor element are connected by a conductive resin.    
     
     
         7 . The semiconductor package as set forth in    claim 5   , 
 wherein the resin layer is disposed so that at least a side surface of the conductive plate being covered.    
     
     
         8 . A semiconductor package, comprising: 
 a wiring substrate having a first face and a second face, the substrate having at least a first connecting pad formed on the first face;    a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type;    at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and    a resin layer disposed on the first face of the wiring substrate and the second face of the semiconductor element so that the semiconductor element being sealed;    wherein, (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, when αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.    
     
     
         9 . The semiconductor package as set forth in    claim 8   , 
 wherein, (αc·Ec)/(αs·Es) is approximately 1.5 or more, when αc is a thermal expansion coefficient of the semiconductor element and Ec is a Young's modulus of the semiconductor element.    
     
     
         10 . The semiconductor package as set forth in    claim 8   , 
 wherein the resin layer for sealing has a first portion filled in between the wiring substrate and the semiconductor element, and a second portion covering the semiconductor element from above the second face of the semiconductor element, and    wherein a Young's modulus of the first portion of the resin is smaller than a Young's Modulus of the second portion of the resin.    
     
     
         11 . The semiconductor package as set forth in    claim 8   ,  
       wherein the resin layer for sealing has a first portion filled in between the wiring substrate and the semiconductor element, and a second portion covering the semiconductor element from above the second face of the semiconductor element, and  
       wherein the first portion and the second portion are formed of an identical resin.  
     
     
         12 . The semiconductor package as set forth in    claim 8   ,  
       wherein the resin forming the first portion and the second portion containing a filler having a distribution of a diameter less than a gap between the wiring substrate and the semiconductor element.  
     
     
         13 . A manufacturing method of a semiconductor package, comprising steps of: 
 mounting a semiconductor element on a first face of a wiring substrate, a first face of the semiconductor having at least a connecting terminal, the first face of the wiring substrate having at least a first connecting pad, the connecting terminal of the semiconductor element being connected by a conductive bump; and    forming a resin layer on the first face of the wiring substrate so that the semiconductor element is sealed;    wherein, αr, Er, Hr, αs, Es, Hs are arranged so that (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, when αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus if the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrates, Es is a Young's modulus of the wiring substrate and Hs is a thickness of the wiring substrates.    
     
     
         14 . The manufacturing method of a semiconductor package as set forth in    claim 13   , 
 wherein the step for forming the resin layer is carried out with transfer mold method.    
     
     
         15 . The manufacturing method of a semiconductor package as set forth in    claim 14   , 
 a resin forming the resin layer containing a filler having a distribution of a diameter less than a gap between the wiring substrate and the semiconductor element.    
     
     
         16 . The manufacturing method of a semiconductor package as set forth in    claim 13   , 
 wherein the a resin forming the resin layer is cured under pressure.