Method for forming an inter-metal dielectric layer
Abstract
A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. An FSG layer is formed on the liner layer by using HDPCVD. A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of forming, an inter-metal dielectric layer, comprising the steps of:
providing a substrate; forming a plurality of wiring lines on the substrate; forming a protective layer on the wiring lines; forming a first undoped silicon glass layer over the wiring lines and over the substrate; forming a fluorinated silicon glass layer on the first undoped silicon glass layer; forming a second undoped silicon glass layer on the fluorinated silicon glass layer; forming a oxide layer on the second undoped silicon glass layer; and polishing the oxide layer to obtain a planarized surface.
2 . The method according to claim 1 , wherein the first undoped silicon glass layer, the fluorinated silicon glass layer and the second undoped silicon glass layer are formed by high density plasma chemical vapor deposition.
3 . The method according to claim 1 , wherein a thickness of the first undoped silicon glass layer is about 100-1000 Å.
4 . The method according to claim 1 , wherein a thickness of the fluorinated silicon glass layer is about 0.9-1.0 times a thickness of the wiring lines.
5 . The method according to claim 1 , wherein a thickness of the second undoped silicon glass layer is about 0.2-0.3 times a thickness of the wiring lines.
6 . The method according to claim 1 , wherein the oxide layer is formed by plasma-enhanced chemical vapor deposition.
7 . A method of forming an inter-metal dielectric layer, comprising the steps of:
providing at least a wiring line on a substrate; forming a conformal liner layer over the wiring line; forming a fluorinated silicon glass layer on the liner layer; forming a cap layer on the fluorinated silicon glass layer; and forming a dielectric layer on the cap layer.
8 . The method according to claim 7 , wherein a thickness of the liner layer is about 100-1000 Å.
9 . The method according to claim 7 , wherein the liner layer comprises undoped silicon glass.
10 . The method according to claim 9 , wherein the liner layer is formed by high density plasma chemical vapor deposition.
11 . The method according to claim 7 , wherein the fluorinated silicon glass layer is formed by high density plasma chemical vapor deposition.
12 . The method according to claim 7 , wherein a thickness of the fluorinated silicon glass layer is about 0.9-1.0 times a thickness of the wiring lines.
13 . The method according to claim 7 , wherein the cap layer comprises undoped silicon glass.
14 . The method according to claim 13 , wherein the cap layer is formed by high density plasma chemical vapor deposition.
15 . The method according to claim 7 , wherein a thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines.
16 . The method according to claim 7 , wherein the dielectric layer comprises silicon oxide.
17 . The method according to claim 16 , wherein the dielectric layer is formed by plasma-enhanced chemical vapor deposition.Join the waitlist — get patent alerts
Track US2001019883A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.