Method of forming contacts

Abstract

A method of forming a contact is disclosed. A substrate having a desired electrical contact location is provided. The substrate has a conductive layer. A first mask with an edge over the desired electrical contact location is formed on the substrate. A contact material is deposited over the first mask and the substrate. A first portion of the contact material is then removed such that a second portion of the contact material remains to form a contact adjacent to the edge of the mask, over the desired electrical contact location.

What is claimed is:  
     
         1 . A method of forming a contact, said method comprising the steps of: 
 providing a substrate having a location where an electrical contact is desired, said substrate having a conductive layer;    forming a first mask over said substrate wherein said first mask has an edge over said location;    depositing a contact material over said substrate and said first mask; and    removing a first portion of said contact material so that a second portion of said contact material remains adjacent to said edge and over said location, defining a contact.    
     
     
         2 . The method of    claim 1   , further comprising the steps of: 
 depositing a dielectric layer over said first mask, said contact, and said substrate; and    removing a top portion of said dielectric layer to reveal said contact.    
     
     
         3 . The method of    claim 2   , wherein siad dielectric layer is a low-k material.  
     
     
         4 . The method of    claim 2   , wherein said step of removing a top portion of said dielectric layer includes chemical mechanical polishing.  
     
     
         5 . The method of    claim 1   , further comprising the steps of: 
 removing said first mask;    depositing a dielectric layer over said contact and said substrate; and    removing a top portion of said dielectric layer to reveal said contact.    
     
     
         6 . The method of    claim 5   , wherein said step of removing a top portion of said dielectric layer includes chemical mechanical polishing.  
     
     
         7 . The method of    claim 5   , wherein said dielectric layer comprises a low dielectric constant material.  
     
     
         8 . The method of    claim 1   , wherein the step of removing a first portion of said contact material comprises the steps of: 
 anisotropic etching said contact material so that the top of said first mask is exposed and a remaining portion of said contact material defines a contact spacer around said first mask;    forming a second mask over said contact spacer to define a contact area over said location; and    etching said contact spacer in alignment with said second mask to form a contact adjacent to said edge and over said location.    
     
     
         9 . The method of    claim 8   , wherein the step of anisotropic etching comprises reactive ion etching.  
     
     
         10 . The method of    claim 1   , wherein removing said contact material comprises the steps of: 
 forming a second mask over said contact material to define a contact area adjacent to said edge; and    etching said contact spacer in alignment with said second mask to form a contact adjacent to said edge and over said location.    
     
     
         11 . The method of    claim 10   , wherein said step of etching comprises anisotropic etch.  
     
     
         12 . The method of    claim 1   , wherein said first mask comprises silicon dioxide.  
     
     
         13 . The method of    claim 1   , wherein said second mask comprises photoresist.  
     
     
         14 . The method of    claim 1   , wherein said contact material and said conductive layer comprise the same material.  
     
     
         15 . The method of    claim 1   , wherein said contact material comprises aluminum.  
     
     
         16 . The method of    claim 1   , wherein said contact has an aspect ratio of at least 3.  
     
     
         17 . A method of forming a contact, said method comprising the steps of: 
 providing a substrate having a conductive layer with a location on which an electrical contact is desired;    forming a mask layer over said substrate;    patterning said mask layer to create a first mask, having an edge over said location;    blanket depositing a conductive contact material over said substrate and said first mask;    anisotropic etching said conductive contact material so that the top of said first mask is exposed and the remaining portion of said conductive contact material forms a contact spacer adjacent to and around said first mask;    forming a second mask over said contact spacer to define a contact area over said location; and    etching said contact spacer to form a contact adjacent to said edge and over said location.    
     
     
         18 . The method of    claim 17   , further comprising the steps of: 
 blanket depositing an interlayer dielectric layer over said first mask, said contact, and said substrate; and    planarizing said interlayer dielectric layer to reveal said contact.    
     
     
         19 . The method of    claim 18   , whereing the interlayer dielectric layer is a low-k material.  
     
     
         20 . The method of    claim 18   , wherein said step of planarizing said interlayer dielectric layer includes chemical mechanical polishing.  
     
     
         21 . The method of    claim 17   , further comprising the steps of: 
 removing said first mask;    blanket depositing an interlayer dielectric layer over said contact and said substrate; and    planarizing said interlayer dielectric layer to reveal said contact.    
     
     
         22 . The method of    claim 21   , wherein said step of planarizing said interlayer dielectric layer includes chemical mechanical polishing.  
     
     
         23 . The method of    claim 21   , wherein said interlayer dielectric layer comprises a low dielectric constant material.  
     
     
         24 . The method of    claim 17   , wherein said step of anisotropic etching comprises reactive ion etching.  
     
     
         25 . The method of    claim 17   , wherein said first mask comprises silicon dioxide.  
     
     
         26 . The method of    claim 17   , wherein said second mask comprises photoresist.  
     
     
         27 . The method of    claim 17   , wherein said conductive contact material and said conductive layer comprise the same material.  
     
     
         28 . The method of    claim 17   , wherein said contact comprises aluminum.  
     
     
         29 . The method of    claim 17   , wherein said contact has an aspect ratio of at least 3.  
     
     
         30 . A method of forming a conductive line and a contact, said method comprising the steps of: 
 providing a substrate;    depositing an underlying dielectric layer over said substrate;    depositing a first conductive layer over said underlying dielectric layer;    forming a first mask over a portion of said first conductive layer, said first mask having an edge;    blanket depositing a second conductive layer over said first conductive layer and said first mask;    forming a second mask over a first portion of said second conductive layer, wherein said first mask and said second mask collectively form a combined mask defining a location for said conductive line and said contact; and    etching said second conductive layer and said first conductive layer in alignment with said combined mask to form said conductive line and said contact.    
     
     
         31 . The method of    claim 30   , further comprising the steps of: 
 removing said second mask to reveal said second conductive layer;    blanket depositing an interlayer dielectric layer over said substrate, said second conductive layer, and said first mask; and    planarizing said interlayer dielectric layer to reveal said contact.    
     
     
         32 . The method of    claim 31   , wherein said interlayer dielectric layer is a low-k material.  
     
     
         33 . The method of    claim 31   , wherein said step of planarizing said interlayer dielectric layer includes chemical mechanical polishing.  
     
     
         34 . The method of    claim 30   , further comprising the steps of: 
 removing said first mask and said second mask;    blanket depositing an interlayer dielectric layer over said substrate, said conductive line, and said contact; and    planarizing said interlayer dielectric layer to reveal said contact.    
     
     
         35 . The method of    claim 32   , wherein said step of planarizing said interlayer dielectric layer includes chemical mechanical polishing.  
     
     
         36 . The method of    claim 32   , wherein said interlayer dielectric layer comprises a low dielectric constant material.  
     
     
         37 . The method of    claim 30   , wherein said first mask comprises silicon dioxide.  
     
     
         38 . The method of    claim 30   , wherein said second mask comprises photoresist.  
     
     
         39 . The method of    claim 30    wherein said first conductive layer and said second conductive layer comprise the same material.  
     
     
         40 . The method of    claim 30   , wherein said second conductive layer comprises aluminum.  
     
     
         41 . An integrated circuit comprising: 
 a dielectric layer formed on a substrate;    a conductive line over said dielectric layer, said conductive line having a first portion and a second portion;    a first dielectric material covering said first portion of said conductive line, said first dielectric material having a side wall;    a conductive contact material covering said second portion of said conductive line and adjacent to said side wall of said first dielectric material; and    a second dielectric material disposed over said conductive contact material, said second dielectric material substantially planer with said contact and said first dielectric material.    
     
     
         42 . The integrated circuit of    claim 41   , wherein said first dielectric material and said second dielectric material comprises the same material.  
     
     
         43 . The integrated circuit of    claim 41   , wherein said material comprises a low dielectric constant material.  
     
     
         44 . The integrated circuit of    claim 41   , wherein said first dielectric material comprises silicon dioxide.