Semiconductor device and method for fabricating the same

Abstract

An insulating film is formed of a carbon-containing silicon dioxide film on a semiconductor substrate. In the insulating film, an interconnect groove is formed. A silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of the interconnect groove. And a metal interconnect is formed on the silicon dioxide layer inside the interconnect groove.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an insulating film formed of a carbon-containing silicon dioxide film on a substrate;    an interconnect groove formed in the insulating film;    a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a density high enough to allow almost no oxygen to pass therethrough; and    a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.    
     
     
         2 . The device of    claim 1   , wherein the silicon dioxide layer has a density of 2.0 g/cm 3  or more.  
     
     
         3 . A semiconductor device comprising: 
 an insulating film formed of a carbon-containing silicon dioxide film on a substrate;    an interconnect groove formed in the insulating film;    a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a small and uniform thickness; and    a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.    
     
     
         4 . The device of    claim 1   , wherein the silicon dioxide layer has a thickness of 20 nm or less.  
     
     
         5 . A method for fabricating a semiconductor device, comprising the steps of: 
 a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate;    b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film;    c) performing a dry etching process using an etching gas containing oxygen, thereby removing a cured layer and forming a silicon dioxide layer on the bottom and side faces of the interconnect groove, the cured layer having been formed in an upper part of the resist pattern as a result of the step b);    d) removing the resist pattern by a wet etching process; and    e) filling the interconnect groove with a metal film to form a metal interconnect.    
     
     
         6 . The method of    claim 5   , wherein the dry etching process is performed within a plasma ambient at a pressure of 13.3 Pa or less.  
     
     
         7 . The method of    claim 6   , wherein the dry etching process is an anisotropic RIE process.  
     
     
         8 . The method of    claim 5   , further comprising the step of removing the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, by a wet etching process.  
     
     
         9 . A method for fabricating a semiconductor device, comprising the steps of: 
 a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate;    b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film;    c) filling the interconnect groove with a resist film;    d) removing a part of the resist film, existing over the interconnect groove, and the resist pattern with a cured layer by a dry etching process using an etching gas containing oxygen, the cured layer having been formed in an upper part of the resist pattern as a result of the step b);    e) removing the other part of the resist film, still existing inside the interconnect groove, by a wet etching process; and    f) filling the interconnect groove with a metal film to form a metal interconnect.    
     
     
         10 . The method of    claim 9   , further comprising the step of performing an anisotropic RIE process between the steps e) and f) within a plasma ambient containing oxygen at a pressure of 13.3 Pa or less to form a silicon dioxide layer on the bottom and side faces of the interconnect groove.