Low temperature thin film transistor fabrication

Abstract

The invention broadens the range of materials and processes that are available for Thin Film Transistor (TFT) devices by providing in the device structure an organic semiconductor layer that is in contact with an inorganic mixed oxide gate insulator involving room temperature processing at up to 150 degrees C. A TFT of the invention has a pentacene semiconductor layer in contact with a barium zirconate titanate gate oxide layer formed on a polycarbonate transparent substrate employing at least one of the techniques of sputtering, evaporation and laser ablation.

What is claimed is:  
     
         1 . In a process of fabricating a low temperature thin film transistor by serial deposition, of at least, a semiconductor layer in contact with a gate insulation layer, on a substrate, the improvement comprising, in combination, the steps of: 
 providing an organic semiconductor material as the material for said semiconductor layer,    providing an inorganic oxide material as the material for said gate material,    depositing one, of said semiconductor layer and said gate insulation layer, on the other, by a process taken from the group of sputtering, spinning, evaporation and laser ablation, at a substrate temperature in the range of about 25 to 150 degrees C.    
     
     
         2 . The process of    claim 1    including the step of: 
 providing, as said substrate, a plastic material.  
 
     
     
         3 . The process of    claim 2    including in said serial deposition of layers the steps of depositing a gate electrode on said substrate and the step of depositing in connection with said semiconductor layer, source and drain electrodes.  
     
     
         4 . The process of    claim 3    wherein said source and drain electrodes are deposited before said semiconductor layer.  
     
     
         5 . The process of    claim 3    wherein said source and drain electrodes are deposited on said semiconductor layer.  
     
     
         6 . The process of    claim 3    wherein said substrate is at least one material taken from the group of polycarbonate, polyethylene terephthalate, silicon, quartz and glass.  
     
     
         7 . The process of    claim 6    wherein said electrodes are of at least one material taken from the group of doped silicon, gold, silver, copper, aluminum, molybdenum, platinum and conducting polymers.  
     
     
         8 . The process of    claim 7    wherein said gate insulation is at least one inorganic oxide taken from the group of inorganic oxides including Ta 2 O 3 , V 2 O 3 , TiO 2 , the ferroelectric insulators Bi 4 Ti 3 O 12 , BaMgF 4 , SrTiO 3 , and the mixed oxides SrBi 2 Ta (1-x) Nb x O 3 , PbZr x Ti (1-x) O 3 , BaZr x Ti (1-x) O 3 , and Ba x Sr (1-x) TiO 3 .  
     
     
         9 . The process of    claim 8    wherein said organic semiconductor layer is of the material pentacene.  
     
     
         10 . The process of fabricating a low temperature in film transistor through serial deposition of layers on a substrate, comprising in combination the steps of: 
 performing said deposition of layers in a temperature range of about 25 to 150 degrees C., and during said deposition    employing at least one room temperature deposition process taken from the group of sputtering, spinning, evaporation and laser ablation, and serially,    depositing a gate electrode on said substrate,    depositing an inorganic oxide gate insulation layer on said substrate and over said gate electrode, and,    depositing an organic semiconductor layer on said gate insulation layer including a step of depositing source and drain electrodes separated by a channel distance.    
     
     
         11 . The process of    claim 10    wherein the step of depositing said source and drain electrodes occurs before said step of depositing said organic semiconducting layer.  
     
     
         12 . The process of    claim 10    wherein the step of depositing said source and drain electrodes occurs after said step of depositing said organic semiconducting layer.  
     
     
         13 . The process of    claim 10    wherein said room temperature deposition process is sputtering.  
     
     
         14 . The process of    claim 13    wherein said organic semiconductor is pentacene.  
     
     
         15 . The process of    claim 14    wherein said gate oxide layer is barium zirconate titanate.  
     
     
         16 . The process of    claim 15    wherein said gate electrode and said source and drain electrodes are of silicon doped to 0.003 ohm cm.  
     
     
         17 . The process of    claim 16    wherein said substrate is a layer of polycarbonate plastic.  
     
     
         18 . A thin film transistor device for processing in fabrication and operation in an about 25 to 150 degree C. temperature range comprising: 
 a substrate on which an electrically conducting gate electrode is positioned,    a layer of inorganic gate insulation positioned on said substrate and over said gate electrode,    a layer of an organic semiconductor positioned in contact with said layer of gate insulation, and,    source and drain electrodes in contact with said organic semiconductor layer in registration with respect to said gate electrode.    
     
     
         19 . The transistor device of    claim 18    where said inorganic gate electrode is barium zirconium titanate with a dielectric constant of at least 15.  
     
     
         20 . The transistor device of    claim 19    wherein said substrate is selected from the group consisting of glass, plastic, and quartz.  
     
     
         21 . The transistor device of    claim 20    wherein the material of said gate and said source and drain electrodes is taken from the group of doped silicon, metals and conducting polymers.  
     
     
         22 . The transistor device of    claim 21    wherein said layer of inorganic gate insulation is at least one inorganic oxide taken from the group of inorganic oxides including Ta 2 O 5 , V 2 O 3 , TiO 2 , the ferroelectric insulators Bi 4 Ti 3 O 12 , BaMgF 4 , SrTiO 3 , and, the mixed oxides SrB 12 Ta (1-x) Nb x O 3 , PbZr x Ti (1-x) O 3 , BaZr (1-x) Ti x O 3 , and Ba x Sr (1-x) Ti O 3 .  
     
     
         23 . The transistor device of    claim 22    wherein said layer of organic semiconductor is the material pentacene.