Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget

Abstract

A method for making a ULSI MOSFET chip includes forming a sacrificial gate on a substrate along with activated source and drain regions, but without initially establishing a doped channel region. The polysilicon portion of the sacrificial gate is then removed and a neutral ion species such as Silicon or Germanium is implanted between the source and drain regions in the region that is to become the doped channel region. A dopant substance is next implanted into the channel region, which is then exposed to ultra-rapid thermal annealing to cause the dopant to form a box-like, super-steep retrograded channel profile. The gate is then re-formed over the now activated doped channel region.

What is claimed is:  
     
         1 . A method for establishing at least one transistor on a semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a source region and a drain region in the substrate and a sacrificial gate above the source and drain regions, without forming a doped channel region between the source and drain regions; then 
 removing the sacrificial gate;  
 implanting at least one neutral ion species in the substrate between the source and drain regions to define an amorphous region;  
 implanting at least one dopant in the amorphous region;  
 heating at least the amorphous region to activate the dopant and thereby establish a doped channel region; and  
 forming a gate above the doped channel region.  
   
     
     
         2 . The method of    claim 1   , wherein the heating step is accomplished by heating the amorphous region to no more than nine hundred fifty degrees Celsius (950° C.).  
     
     
         3 . The method of    claim 2   , wherein the heating step is accomplished by heating the amorphous region to no more than nine hundred degrees Celsius (900° C.).  
     
     
         4 . The method of    claim 1   , wherein the heating step is accomplished by laser annealing.  
     
     
         5 . The method of    claim 4   , wherein the heating step is accomplished by irradiating the amorphous region with a laser for no more than ten nanoseconds.  
     
     
         6 . The method of    claim 5   , wherein the heating step is accomplished by irradiating the amorphous region with a laser for no more than five nanoseconds.  
     
     
         7 . The method of    claim 4   , wherein the heating step is accomplished by irradiating the amorphous region with a laser such that the temperature of the amorphous region does not exceed nine hundred fifty degrees Celsius (950° C.).  
     
     
         8 . The method of    claim 1   , wherein the neutral ion species includes at least one of: Silicon (Si) and Germanium (Ge).  
     
     
         9 . A semiconductor device made according to    claim 1   .  
     
     
         10 . A digital processing apparatus incorporating the device of    claim 9   .  
     
     
         11 . A method for making an ultra-large scale integration (ULSI) semiconductor device, comprising: 
 forming source and drain regions in a semiconductor substrate using a first activation temperature; then 
 forming a doped channel region between the source and drain regions using a second activation temperature less than the first activation temperature.  
   
     
     
         12 . The method of    claim 11   , wherein the second activation temperature is induced by irradiating a portion of the substrate with a laser for less than ten nanoseconds such that the second temperature does not exceed nine hundred fifty degrees Celsius (950° C.).  
     
     
         13 . The method of    claim 12   , wherein the second activation temperature is induced by irradiating a portion of the substrate with a laser for less than five nanoseconds such that the second temperature does not exceed nine hundred degrees Celsius (900° C.).  
     
     
         14 . The method of    claim 11   , further comprising: 
 implanting at least one neutral ion species in the substrate between the source and drain regions to define an amorphous region;    implanting at least one dopant in the amorphous region;    heating at least the amorphous region to the second activation temperature to activate the dopant and thereby establish a doped channel region; and    forming a gate above the doped channel region.    
     
     
         15 . The method of    claim 14   , wherein the neutral ion species includes at least one of: Silicon (Si) and Germanium (Ge).  
     
     
         16 . A semiconductor device made according to    claim 11   .  
     
     
         17 . A digital processing apparatus incorporating the device of    claim 16   .  
     
     
         18 . A semiconductor device including: 
 at least one semiconductor substrate;    at least one transistor gate on the substrate;    source and drain regions in the substrate below the gate;    a channel region between the source region and the drain region;    at least one activated dopant implant in the channel region; and    at least one neutral ion species implanted in the dopant region.    
     
     
         19 . A digital processing apparatus incorporating the device of    claim 18   .